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参数资料
| 型号： | 74LVC543ADB,112 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 1/20页 |
| 文件大小： | 0K |
| 描述： | IC REGISTERED TXRX 8BIT 24SSOP |
| 产品培训模块： | Logic Packages |
| 标准包装： | 59 |
| 系列： | 74LVC |
| 逻辑类型： | 寄存收发器，非反相 |
| 元件数： | 1 |
| 每个元件的位元数： | 8 |
| 输出电流高，低： | 24mA，24mA |
| 电源电压： | 1.2 V ~ 3.6 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 24-SSOP |
| 包装： | 管件 |
| 其它名称： | 74LVC543ADB 74LVC543ADB-ND 935245860112 |
1.
General description
The 74LVC543A is an octal registered transceiver containing two sets of D-type latches
for temporary storage of the data flow in either direction. Separate latch enable inputs
(pins LEAB and LEBA) and output enable inputs (pins OEAB and OEBA), are provided for
each register. The separate inputs permit independent control of input and output in either
direction of the data flow.
The 74LVC543A contains eight D-type latches, with separate inputs and controls for each
set. For data flow from pins A to B, the A to B enable input (pin EAB) must be LOW. The
LOW state enables data entry from pins A0 to A7 or from pins B0 to B7, as indicated in
Table 3. With pin EAB LOW, a LOW signal on the A to B latch enable input (pin LEAB)
makes the A to B latches transparent. A subsequent LOW-to-HIGH transition on pin LEAB
puts the A data into the latches where it is stored. The B outputs no longer change with
the A inputs. With pins EAB and OEAB both LOW, the 3-state B output buffers are active
and display the data present at the outputs of the A latches.
2.
Features and benefits
5 V tolerant inputs/ouputs for interfacing with 5 V logic
Supply voltage range from 1.2 V to 3.6 V
CMOS low-power consumption
Direct interface with TTL levels
8-bit positive transceiver with D-type latch
Back-to-back registers for storage
Separate controls for data flow in each direction
3-state non-inverting outputs for bus-oriented applications
High-impedance when VCC = 0 V
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from
40 C to +85 C and 40 C to +125 C
74LVC543A
Octal D-type registered transceiver; 3-state
Rev. 8 — 18 December 2012
Product data sheet
相关PDF资料 |
PDF描述 |
|---|---|
| 74LVC543ADB,118 | IC REGISTERED TXRX 8BIT 24SSOP |
| 282817-3 | TERM BLOCK HEADER R/A 3POS 10MM |
| 1776148-5 | TERM BLOCK HEADER 5POS R/A SHRD |
| 282828-3 | TERM BLOCK HEADER VERT 3POS .4" |
| 1776147-3 | TERM BLOCK HEADER 3POS SHROUDED |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 74LVC543ADB-T | 功能描述:总线收发器 OCTAL REG XCVR 3-S RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
| 74LVC543AD-T | 功能描述:总线收发器 OCTAL REG XCVR 3-S RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
| 74LVC543APW | 功能描述:总线收发器 3.3V OCTAL REG XCVR 3-S RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
| 74LVC543APW,112 | 功能描述:总线收发器 3.3V OCTAL REG XCVR RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
| 74LVC543APW,118 | 功能描述:总线收发器 3.3V OCTAL REG XCVR RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
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