参数资料
型号: 74LVC74ADB,112
厂商: NXP Semiconductors
文件页数: 1/19页
文件大小: 0K
描述: IC DUAL D FF POS-EDGE 14SSOP
产品培训模块: Logic Packages
标准包装: 78
系列: 74LVC
功能: 设置(预设)和复位
类型: D 型
输出类型: 差分
元件数: 2
每个元件的位元数: 1
频率 - 时钟: 250MHz
延迟时间 - 传输: 2.5ns
触发器类型: 正边沿
输出电流高,低: 24mA,24mA
电源电压: 1.2 V ~ 3.6 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 14-SSOP(0.209",5.30mm 宽)
包装: 管件
其它名称: 74LVC74ADB
74LVC74ADB-ND
935260735112
1.
General description
The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs,
clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs.
The set and reset are asynchronous active LOW inputs and operate independently of the
clock input. Information on the data input is transferred to the nQ output on the
LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time
prior to the LOW-to-HIGH clock transition, for predictable operation.
Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and
fall times.
2.
Features and benefits
5 V tolerant inputs for interlacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from
40 C to +85 C and 40 C to +125 C
74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
Rev. 7 — 20 November 2012
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