参数资料
型号: 74LVT652PW,112
厂商: NXP Semiconductors
文件页数: 9/14页
文件大小: 0K
描述: IC TRANSCVR 8BIT N-INV 24TSSOP
产品培训模块: Logic Packages
标准包装: 63
系列: 74LVT
逻辑类型: 收发器,非反相
元件数: 1
每个元件的位元数: 8
输出电流高,低: 32mA,64mA
电源电压: 2.7 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 24-TSSOP
包装: 管件
其它名称: 74LVT652PW
74LVT652PW-ND
935177740112
Philips Semiconductors
Product specification
74LVT652
3.3V Octal transceiver/register, non-inverting
(3-State)
1998 Feb 19
4
The following examples demonstrate the four fundamental
bus-management functions that can be performed with the
74LVT652.
The select pins determine whether data is stored or transferred
through the device in real time.
The output enable pins determine the direction of the data flow.
}
REAL TIME BUS TRANSFER
BUS B TO BUS A
OEAB OEBA CPAB CPBA SAB
SBA
LL
X
L
}
REAL TIME BUS TRANSFER
BUS A TO BUS B
OEAB OEBA CPAB CPBA SAB
SBA
HH
X
L
X
}
STORAGE FROM
A, B, OR A AND B
OEAB OEBA CPAB CPBA SAB
SBA
XH
XXX
LX
X
XX
LH
↑↑
XX
}
TRANSFER STORED DATA
TO A OR B
OEAB OEBA CPAB CPBA SAB
SBA
H
L
H | L H | L
H
A
B
SV00055
FUNCTION TABLE
INPUTS
DATA I/O
OPERATING MODE
OEAB
OEBA
CPAB
CPBA
SAB
SBA
An
Bn
OPERATING MODE
L
H
H or L
H or L
X
Input
Isolation
Store A and B data
X
H
H or L
X
**
X
Input
Unspecified**
Output*
Store A, Hold B
Store A in both registers
L
X
L
H or L
X
**
Unspecified**
Output*
Input
Hold A, Store B
Store B in both registers
L
X
H or L
X
L
H
Output
Input
Real time B data to A bus
Stored B data to A bus
H
X
H or L
X
L
H
X
Input
Output
Real time A data to B bus
Store A data to B bus
H
L
H or L
H
Output
Stored A data to B bus
Stored B data to A bus
H = High voltage level
L
= Low voltage level
X = Don’t care
↑ = Low-to-High clock transition
*
The data output function may be enabled or disabled by various signals at the OEBA and OEAB inputs. Data input functions are always
enabled, i.e., data at the bus pins will be stored on every Low-to-High transition of the clock.
**
If both Select controls (SAB and SBA) are Low, then clocks can occur simultaneously. If either Select control is High, the clocks must be
staggered in order to load both registers.
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