参数资料
型号: 74LVX132SJ
厂商: Fairchild Semiconductor
文件页数: 1/9页
文件大小: 0K
描述: IC GATE NAND QUAD 2 SCHM 14SOP
标准包装: 47
系列: 74LVX
逻辑类型: 与非门
电路数: 4
输入数: 2
特点: 施密特触发器
电源电压: 2 V ~ 3.6 V
电流 - 静态(最大值): 2µA
输出电流高,低: 4mA,4mA
逻辑电平 - 低: 0.9V
逻辑电平 - 高: 2.2V
额定电压和最大 CL 时的最大传播延迟: 15.4ns @ 3V ~ 3.6V,50pF
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
供应商设备封装: 14-SOIC
封装/外壳: 14-SOIC(0.209",5.30mm 宽)
包装: 管件
74L
VX132
Lo
w
V
olta
g
e
Quad
2-Input
NAND
Sc
hmitt
T
rig
g
e
r
1996 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74LVX132 Rev. 1.4.0
February 2008
74LVX132
Low Voltage Quad 2-Input NAND Schmitt Trigger
Features
Input voltage level translation from 5V to 3V
Ideal for low power/low noise 3.3V applications
Guaranteed simultaneous switching noise level and
dynamic threshold performance
General Description
The LVX132 contains four 2-input NAND Schmitt Trigger
Gates. The pin configuration and function are the same
as the LVX00 but the inputs have hysteresis between the
positive-going and negative-going input thresholds,
which are capable of transforming slowly changing input
signals into sharply defined, jitter-free output signals,
thus providing greater noise margins than conventional
gates.
The inputs tolerate voltages up to 7V allowing the inter-
face of 5V systems to 3V systems.
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Order
Number
Package
Number
Package Description
74LVX132M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LVX132SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVX132MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
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