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| 型号： | 74LVX161284MEAX |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 7/11页 |
| 文件大小： | 0K |
| 描述： | TXRX TRANSLATING IEEE 48SSOP |
| 产品变化通告： | Die Material/Mold Compound Change 10/Sept/2008 |
| 标准包装： | 1,000 |
| 系列： | 74LVX |
| 逻辑类型： | IEEE STD 1284 转换收发器 |
| 电源电压： | 3 V ~ 3.6 V |
| 位数： | 8 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-BSSOP（0.295"，7.50mm 宽） |
| 供应商设备封装： | 48-SSOP |
| 包装： | 带卷 (TR) |
5
www.fairchildsemi.com
7
4
L
VX16
1284
AC Electrical Characteristics
Note 8: Open Drain
Note 9: tSKEW is measured for common edge output transitions and compares the measured propagation delay for a given path type:
(i) A1–A8 to B1–B8, A9–A13 to Y9–Y13
(ii) B1–B8 to A1–A8
(iii) C14–C17 to A14–A17
Note 10: This parameter is guaranteed but not tested, characterized only.
Capacitance
Note 11: CI/O is measured at frequency 1 MHz, per MIL-STD-883B, Method 3012
Symbol
Parameter
TA 0qC to 70qCTA 40qC to 85qC
Units
Figure
Number
VCC 3.0V–3.6V
VCC—Cable 3.0V–5.5V
Min
Max
Min
Max
tPHL
A1–A8 to B1–B8
2.0
40.0
2.0
44.0
ns
Figure 1
tPLH
A1–A8 to B1–B8
2.0
40.0
2.0
44.0
ns
Figure 2
tPHL
B1–B8 to A1–A8
2.0
40.0
2.0
44.0
ns
Figure 3
tPLH
B1–B8 to A1–A8
2.0
40.0
2.0
44.0
ns
Figure 3
tPHL
A9–A13 to Y9–Y13
2.0
40.0
2.0
44.0
ns
Figure 1
tPLH
A9–A13 to Y9–Y13
2.0
40.0
2.0
44.0
ns
Figure 2
tPHL
C14–C17 to A14–A17
2.0
40.0
2.0
44.0
ns
Figure 3
tPLH
C14–C17 to A14–A17
2.0
40.0
2.0
44.0
ns
Figure 3
tSKEW
LH-LH or HL-HL
10.0
12.0
ns
(Note 9)
tPHL
PLHIN to PLH
2.0
40.0
2.0
44.0
ns
Figure 1
tPLH
PLHIN to PLH
2.0
40.0
2.0
44.0
ns
Figure 2
tPHL
HLHIN to HLH
2.0
40.0
2.0
44.0
ns
Figure 3
tPLH
HLHIN to HLH
2.0
40.0
2.0
44.0
ns
Figure 3
tPHZ
Output Disable Time
2.0
15.0
2.0
18.0
ns
Figure 7
tPLZ
DIR to A1–A8
2.0
15.0
2.0
18.0
tPZH
Output Enable Time
2.0
50.0
2.0
50.0
ns
Figure 8
tPZL
DIR to A1–A8
2.0
50.0
2.0
50.0
tPHZ
Output Disable Time
2.0
50.0
2.0
50.0
ns
Figure 9
tPLZ
DIR to B1–B8
2.0
50.0
2.0
50.0
tpEN
Output Enable Time
2.0
25.0
2.0
28.0
ns
Figure 2
HD to B1–B8, Y9–Y13
2.0
25.0
2.0
28.0
tpDIS
Output Disable Time
2.0
25.0
2.0
28.0
ns
Figure 2
HD to B1–B8, Y9–Y13
2.0
25.0
2.0
28.0
tpEN–tpDIS
Output Enable-
10.0
12.0
ns
Output Disable
tSLEW
Output Slew Rate
tPLH
B1–B8, Y9–Y13
0.05
0.40
0.05
0.40
V/ns
Figure 5
tPHL
0.05
0.40
0.05
0.40
Figure 4
tr, tf
tRISE and tFALL
120
ns
Figure 6
B1–B8 (Note 8),
120
(Note 10)
Y9–Y13 (Note 8)
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
3
pF
VCC 0.0V (HD, DIR, A9–A13, C14–C17, PLHIN and HLHIN)
CI/O (Note 11)
I/O Pin Capacitance
5
pF
VCC 3.3V
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