参数资料
型号: 74LVX273SJ
厂商: Fairchild Semiconductor
文件页数: 1/7页
文件大小: 0K
描述: IC FLIP FLOP OCT D LV 20SOP
标准包装: 38
系列: 74LVX
功能: 主复位
类型: D 型总线
输出类型: 非反相
元件数: 1
每个元件的位元数: 8
频率 - 时钟: 150MHz
延迟时间 - 传输: 7.1ns
触发器类型: 正边沿
输出电流高,低: 4mA,4mA
电源电压: 2 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-SOIC(0.209",5.30mm 宽)
包装: 管件
2005 Fairchild Semiconductor Corporation
DS011614
www.fairchildsemi.com
June 1993
Revised April 2005
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74LVX273
Low Voltage Octal D-Type Flip-Flop
General Description
The LVX273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) input load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements. The inputs tolerate up to 7V allowing
interface of 5V systems to 3V systems.
Features
s Input voltage translation from 5V to 3V
s Ideal for low power/low noise 3.3V applications
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Devices also available in Tape and Reel. Specify by appending letter suffix “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbols
IEEE/IEC
Pin Descriptions
Connection Diagram
Truth Table
H
HIGH Voltage Level
X
Immaterial
L
LOW Voltage Level
LOW-to-HIGH Transition
Order Number
Package Number
Package Description
74LVX273M
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LVX273SJ
M20D
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVX273MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names
Description
D0–D7
Data Inputs
MR
Master Reset
CP
Clock Pulse Input
Q0–Q7
Data Outputs
Operating Mode
Inputs
Outputs
MR
CP
Dn
Qn
Reset (Clear)
L
X
L
Load '1'
H
HH
Load '0'
H
LL
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