参数资料
型号: 74LVX74SJX
厂商: Fairchild Semiconductor
文件页数: 1/9页
文件大小: 0K
描述: IC FLIP FLOP DUAL D POS 14SOP
标准包装: 2,000
系列: 74LVX
功能: 设置(预设)和复位
类型: D 型
输出类型: 差分
元件数: 2
每个元件的位元数: 1
频率 - 时钟: 95MHz
延迟时间 - 传输: 5.7ns
触发器类型: 正边沿
输出电流高,低: 4mA,4mA
电源电压: 2 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 14-SOIC(0.209",5.30mm 宽)
包装: 带卷 (TR)
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Flip-Flop
1993 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74LVX74 Rev. 1.4.0
February 2008
74LVX74
Low Voltage Dual D-Type Positive Edge-Triggered
Flip-Flop
Features
Input voltage level translation from 5V to 3V
Ideal for low power/low noise 3.3V applications
Guaranteed simultaneous switching noise level and
dynamic threshold performance
General Description
The LVX74 is a dual D-type flip-flop with Asynchronous
Clear and Set inputs and complementary (Q, Q) outputs.
Information at the input is transferred to the outputs on
the positive edge of the clock pulse. After the Clock
Pulse input threshold voltage has been passed, the Data
input is locked out and information present will not be
transferred to the outputs until the next rising edge of the
Clock Pulse input.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and
Q HIGH
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Order
Number
Package
Number
Package Description
74LVX74M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LVX74SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVX74MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
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