参数资料
型号: 74VCX08MTCX
厂商: Fairchild Semiconductor
文件页数: 7/11页
文件大小: 0K
描述: IC GATE AND QUAD 2IN LV 14TSSOP
标准包装: 1
系列: 74VCX
逻辑类型: 与门
电路数: 4
输入数: 2
电源电压: 1.2 V ~ 3.6 V
电流 - 静态(最大值): 20µA
输出电流高,低: 24mA,24mA
逻辑电平 - 低: 0.7 V ~ 0.8 V
逻辑电平 - 高: 1.6 V ~ 2 V
额定电压和最大 CL 时的最大传播延迟: 2.8ns @ 3.3V,30pF
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
供应商设备封装: 14-TSSOP
封装/外壳: 14-TSSOP(0.173",4.40mm 宽)
包装: 标准包装
其它名称: 74VCX08MTCXDKR
IDT / ICS LVCMOS/LVTTL FANOUT BUFFER
5
ICS8304AM REV. H OCTOBER 29, 2010
ICS8304
LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER
ADDITIVE PHASE JITTER
Additive Phase Jitter @ 125MHz
(12kHz to 20MHz) = 0.173ps typical
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
As with most timing specifications, phase noise measurements
has issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The device
band to the power in the fundamental. When the required offset
is specified, the phase noise is called a
dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
meets the noise floor of what is shown, but can actually be lower.
The phase noise is dependant on the input source and
measurement equipment.
OFFSET FROM CARRIER FREQUENCY (HZ)
SSB
P
HASE
N
OISE
dB
c
/H
Z
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