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| 型号： | 74VCX164245MTDX |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 1/9页 |
| 文件大小： | 0K |
| 描述： | IC TRANSCEIVER 16BIT 48TSSOP |
| 产品培训模块： | Logic Translator Solutions |
| 标准包装： | 1 |
| 系列： | 74VCX |
| 逻辑类型： | 收发器，非反相 |
| 元件数： | 2 |
| 每个元件的位元数： | 8 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-TFSOP（0.240"，6.10mm 宽） |
| 供应商设备封装： | 48-TSSOP |
| 包装： | 标准包装 |
| 其它名称： | 74VCX164245MTDXDKR |
2005 Fairchild Semiconductor Corporation
DS500159
www.fairchildsemi.com
March 2000
Revised June 2005
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74VCX164245
Low Voltage 16-Bit Dual Supply Translating Transceiver
with 3-STATE Outputs
General Description
The VCX164245 is a dual supply, 16-bit translating trans-
ceiver that is designed for two way asynchronous commu-
nication between busses at different supply voltages by
providing true signal translation. The supply rails consist of
VCCB, which is the higher potential rail operating at 2.3V to
3.6V and VCCA, which is the lower potential rail operating at
1.65V to 2.7V. (VCCA must be less than or equal to VCCB
for proper device operation.) This dual supply design
allows for translation from 1.8V to 2.5V busses to busses at
a higher potential, up to 3.3V.
The Transmit/Receive (T/R) input determines the direction
of data flow. Transmit (active-HIGH) enables data from A
Ports to B Ports. Receive (active-LOW) enables data from
B Ports to A Ports. The Output Enable (OE) input, when
HIGH, disables both A and B Ports by placing them in a
High-Z condition. The A Port interfaces with the lower volt-
age bus (1.8V
2.5V). The B Port interfaces with the
higher voltage bus (2.7V
3.3V). Also the VCX164245 is
designed so that the control pins (T/Rn, OEn) are supplied
by VCCB.
The 74VCX164245 is suitable for mixed voltage applica-
tions such as notebook computers using a 1.8V CPU and
3.3V peripheral components. It is fabricated with an
Advanced CMOS technology to achieve high speed opera-
tion while maintaining low CMOS power dissipation.
Features
s Bidirectional interface between busses ranging from
1.65V to 3.6V
s Supports Live Insertion and Withdrawal (Note 1)
s Static Drive (IOH/IOL)
r24 mA @ 3.0V VCC
r18 mA @ 2.3V VCC
r6 mA @ 1.65V VCC
s Functionally compatible with 74 series 16245
s Latchup performance exceeds 300 mA
s ESD performance:
Human Body Model
!2000V
Machine model
!200V
s Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Note 1: To ensure the high impedance state during power up or power
down, OEn should be tied to VCCB through a pull up resistor. The minimum
value of the resistor is determined by the current sourcing capability of the
driver.
Ordering Code:
Note 2: Ordering Code “G” indicates Trays.
Note 3: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Diagram
Order Number
Package Number
Package Description
74VCX164245G
(Note 2)(Note 3)
BGA54A
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
74VCX164245MTD
(Note 3)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
s Uses proprietary noise/EMI reduction circuitry
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 74VCX16500 | 制造商:FAIRCHILD 制造商全称:Fairchild Semiconductor 功能描述:Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs |
| 74VCX16500_04 | 制造商:FAIRCHILD 制造商全称:Fairchild Semiconductor 功能描述:Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs |
| 74VCX16500_ZAA30062 WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| 74VCX16500MTD | 功能描述:总线收发器 18-Bit Univ Bus Tran RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
| 74VCX16500MTD_Q | 功能描述:总线收发器 18-Bit Univ Bus Tran RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
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