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参数资料
| 型号： | 74VCX245WMX |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 11/11页 |
| 文件大小： | 0K |
| 描述： | IC TRANSCVR BIDIRECT LV 20SOIC |
| 标准包装： | 1 |
| 系列： | 74VCX |
| 逻辑类型： | 收发器，非反相 |
| 元件数： | 1 |
| 每个元件的位元数： | 8 |
| 输出电流高，低： | 24mA，24mA |
| 电源电压： | 1.4 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 20-SOIC |
| 包装： | 标准包装 |
| 其它名称： | 74VCX245WMXDKR |
9
INDUSTRIAL TEMPERATURERANGE
IDT72V73260 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
Figure 1. Example for Frame Alignment Measurement
TABLE 7 — FRAME ALIGNMENT REGISTER (FAR) BITS
0123
4
5
6
7
8
9
10
11
12
13
14
15
16
ST-BUS Frame
C32i
Offset Value
FE Input
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
GCI Frame
C32i
Offset Value
FE Input
(FD[11:0] = 06H)
(FD12 = 0, sample at CLK LOW phase)
(FD[11:0] = 09H)
(FD12 = 1, sample at CLK HIGH phase)
5932 drw04
Bit
Name
Description
15-14
Unused
Must be zero for normal operation
13
CFE (Complete
When Complete Frame Evaluation = 1, the Frame Evaluation is completed and bits FD12 to FD0 bits contains a valid frame alignment offset.
Frame Evaluation)
This bit is reset to zero, when Start Frame Evaluation bit in the Control Register is changed from 1 to 0.
12
FD12
The falling edge of Frame Evaluation (or rising edge for GCI mode) is sampled during the C32i-HIGH phase (FD12 = 1) or during the
(Frame Delay Bit 12) C32i-LOWphase(FD12=0).ThisbitallowsthemeasurementresolutiontoC32icycle.ThisbitisresettozerowhentheStartFrameEvaluation
bit of the Control Register changes from 1 to 0.
11-0
FD11-0
The binary value expressed in these bits refers to the measured input offset value. These bits are reset to zero when the Start Frame Evaluation
(Frame Delay Bits)
bit of the Control Register changes from 1 to 0. (FD11 – MSB, FD0 – LSB)
Reset Value:
0000H.
15
14
13
12
11
10
9876543210
0
CFE
FD12
FD11
FD10
FD9
FD8
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
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