参数资料
型号: 74VHC08MTR
厂商: 意法半导体
英文描述: Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 14-TSSOP -40 to 85
中文描述: 四2输入与门
文件页数: 4/8页
文件大小: 148K
代理商: 74VHC08MTR
74VHC08
4/8
CAPACITIVE CHARACTERISTICS
1) C
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/4 (per gate)
DYNAMIC SWITCHING CHARACTERISTICS
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 5.0V. Inputs under test switching: 5.0V to threshold (V
ILD
), 0V to threshold
(V
IHD
), f=1MHz.
Symbol
Parameter
Test Condition
Value
Unit
T
A
= 25°C
-40 to 85°C
-55 to 125°C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
C
IN
C
PD
Input Capacitance
Power Dissipation
Capacitance
(note 1)
6
10
10
10
pF
15
pF
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25°C
-40 to 85°C
-55 to 125°C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
OLP
Dynamic Low
Voltage Quiet
Output (note 1, 2)
Dynamic High
Voltage Input
(note 1, 3)
Dynamic Low
Voltage Input
(note 1, 3)
5.0
C
L
= 50 pF
0.3
0.8
V
V
OLV
-0.8
-0.3
V
IHD
5.0
3.5
V
V
ILD
5.0
1.5
V
相关PDF资料
PDF描述
74VHC08T Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 14-TSSOP -40 to 85
74VHC08 Quad 2-Input AND Gate
74VHC08M Quad 2-Input AND Gate
74VHC08N Quad 2-Input AND Gate
74VHC08SJ Quad 2-Input AND Gate
相关代理商/技术参数
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