参数资料
型号: 74VHC125
厂商: 意法半导体
英文描述: Quad Bus Buffers (3-State)(四总线缓冲器)
中文描述: 四总线缓冲器(三态)(四总线缓冲器)
文件页数: 4/8页
文件大小: 69K
代理商: 74VHC125
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Test Conditions
Value
Unit
T
A
= 25
o
C
Min.
Typ.
-40 to 85
o
C
Min.
Max.
10
Max.
10
C
IN
C
OUT
C
PD
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance (note 1)
1) C
PD
isdefined as the value ofthe IC’s internalequivalent capacitance which iscalculated fromtheoperating currentconsumption without load. (Refer to
Test Circuit).Average operting currentcan be obtained by the followingequation. I
CC
(opr) =C
PD
V
CC
f
IN
+I
CC
/4(percircuit)
4
6
pF
pF
pF
14
TEST CIRCUIT
TEST
SWITCH
Open
V
CC
GND
t
PLH
, t
PHL
t
PZL
, t
PLZ
t
PZH
, t
PHZ
C
L
=15/50 pF orequivalent (includes jigand probe capacitance)
R
L
=R
1
=1K
orequivalent
R
T
=Z
OUT
of pulse generator (typically50
)
DYNAMIC SWITCHING CHARACTERISTICS
Symbol
Parameter
Test Conditions
V
CC
(V)
Value
Unit
T
A
= 25
o
C
Min.
Typ.
-40 to 85
o
C
Min.
Max.
0.8
Max.
V
OLP
V
OLV
V
IHD
Dynamic Low Voltage
Quiet Output (note 1, 2)
5.0
C
L
= 50 pF
0.3
-0.3
V
-0.8
3.5
Dynamic High Voltage
Input (note 1, 3)
Dynamic Low Voltage
Input (note 1, 3)
1) Worstcase package.
2) Max number of outputs defined as (n). Datainputsare driven 0V to5.0V, (n-1)outputs switchingand one output at GND.
3) Max number of data inputs (n)switching. (n-1)switching 0V to5.0V.Inputs under testswitching: 5.0Vtothreshold (V
ILD
),0V tothreshold (V
IHD
),f=1MHz.
5.0
V
ILD
5.0
1.5
74VHC125
4/8
相关PDF资料
PDF描述
74VHC126M Quadruple 2-Input Exclusive-OR Gates 14-SOIC -40 to 85
74VHC126T Quadruple 2-Input Exclusive-OR Gates 14-SOIC -40 to 85
74VHC126 Quad Bus Buffers (3-State)(四总线缓冲器)
74VHC132T Quadruple 2-Input Exclusive-OR Gates 14-TSSOP -40 to 85
74VHC132M Quadruple 2-Input Exclusive-OR Gates 14-SOIC -40 to 85
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