参数资料
型号: 74VHC125SJX
厂商: Fairchild Semiconductor
文件页数: 1/9页
文件大小: 0K
描述: IC BUFF TRI-ST QD N-INV 14SOP
标准包装: 2,000
系列: 74VHC
逻辑类型: 缓冲器/线路驱动器,非反相
元件数: 4
每个元件的位元数: 1
输出电流高,低: 8mA,8mA
电源电压: 2 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 14-SOIC(0.209",5.30mm 宽)
供应商设备封装: 14-SOIC
包装: 带卷 (TR)
74VHC125
Quad
Buff
er
with
3-ST
A
TE
Outputs
1993 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74VHC125 Rev. 1.4.0
December 2007
74VHC125
Quad Buffer with 3-STATE Outputs
Features
High Speed: tPD = 3.8ns (Typ.) at VCC = 5V
Lower power dissipation: ICC = 4 A (Max.) at
TA = 25°C
High noise immunity: VNIH = VNIL = 28% VCC (Min.)
Power down protection is provided on all inputs
Low noise: VOLP = 0.8V (Max.)
Pin and function compatible with 74HC125
General Description
The VHC125 contains four independent non-inverting
buffers with 3-STATE outputs. It is an advanced high-
speed CMOS device fabricated with silicon gate CMOS
technology and achieves the high-speed operation simi-
lar to equivalent Bipolar Schottky TTL while maintaining
the CMOS low power dissipation.
An input protection circuit insures that 0V to 7V can be
applied to the input pins without regard to the supply
voltage. This device can be used to interface 5V to 3V
systems and two supply systems such as battery
backup. This circuit prevents device destruction due to
mismatched supply and input voltages.
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Order Number
Package
Number
Package Description
74VHC125M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
74VHC125SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC125MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
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