参数资料
| 型号： | 74VHC161SJ |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 4/11页 |
| 文件大小： | 0K |
| 描述： | IC COUNTER BINARY 4BIT 16SOP |
| 标准包装： | 47 |
| 系列： | 74VHC |
| 逻辑类型： | 二进制计数器 |
| 方向： | 上 |
| 元件数： | 1 |
| 每个元件的位元数： | 4 |
| 复位： | 异步 |
| 计时： | 同步 |
| 计数速率： | 125MHz |
| 触发器类型： | 正边沿 |
| 电源电压： | 2 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.209"，5.30mm 宽） |
| 供应商设备封装： | 16-SOP |
| 包装： | 管件 |
74VHC161
4-Bit
Binar
y
Counter
with
Async
hr
onous
Clear
1993 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74VHC161 Rev. 1.4
2
Logic Symbols
IEEE/IEC
Functional Description
The VHC161 counts in modulo-16 binary sequence.
From state 15 (HHHH) it increments to state 0 (LLLL).
The clock inputs of all flip-flops are driven in parallel
through a clock buffer. Thus all changes of the Q outputs
(except due to Master Reset of the VHC161) occur as a
result of, and synchronous with, the LOW-to-HIGH tran-
sition of the CP input signal. The circuits have four fun-
damental modes of operation, in order of precedence:
asynchronous reset, parallel load, count-up and hold.
Five control inputs—Master Reset, Parallel Enable (PE),
Count Enable Parallel (CEP) and Count Enable Trickle
(CET)—determine the mode of operation, as shown in
the Mode Select Table. A LOW signal on MR overrides
all other inputs and asynchronously forces all outputs
LOW. A LOW signal on PE overrides counting and
allows information on the Parallel Data (Pn) inputs to be
loaded into the flip-flops on the next rising edge of CP.
With PE and MR HIGH, CEP and CET permit counting
when both are HIGH. Conversely, a LOW signal on
either CEP or CET inhibits counting.
The VHC161 uses D-type edge-triggered flip-flops and
changing the PE, CEP and CET inputs when the CP is in
either state does not cause errors, provided that the rec-
ommended setup and hold times, with respect to the ris-
ing edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is
HIGH and counter is in state 15. To implement synchro-
nous multistage counters, the TC outputs can be used
with the CEP and CET inputs in two different ways.
Figure 1 shows the connections for simple ripple carry, in
which the clock period must be longer than the CP to TC
delay of the first stage, plus the cumulative CET to TC
delays of the intermediate stages, plus the CET to CP
setup time of the last stage. This total delay plus setup
time sets the upper limit on clock frequency. For faster
clock rates, the carry lookahead connections shown in
Figure 2 are recommended. In this scheme the ripple
delay through the intermediate stages commences with
the same clock that causes the first stage to tick over
from max to min to start its final cycle. Since this final
cycle requires 16 clocks to complete, there is plenty of
time for the ripple to progress through the intermediate
stages. The critical timing that limits the clock period is
the CP to TC delay of the first stage plus the CEP to CP
setup time of the last stage. The TC output is subject to
decoding spikes due to internal race conditions and is
therefore not recommended for use as a clock or asyn-
chronous reset for flip-flops, registers or counters.
Logic Equations:
Count Enable
= CEP CET PE
TC
= Q0 Q1 Q2 Q3 CET
Figure 1. Multistage Counter with Ripple Carry
Figure 2. Multistage Counter with Lookahead Carry
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