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参数资料
| 型号： | 74VHC4046MTCX |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | XO, clock |
| 英文描述： | Code Hopping Encoder 3.5- 13V, -40C to +85C, 8-SOIC 150mil, T/R |
| 中文描述： | PHASE LOCKED LOOP, 12 MHz, PDSO16 |
| 封装： | 4.40 MM, MO-153, TSSOP-16 |
| 文件页数： | 8/14页 |
| 文件大小： | 283K |
| 代理商： | 74VHC4046MTCX |
Comparator I
Comparator II & III
R
2
e
%
R
2
i
%
R
2
e
%
R
2
i
%
–Given: f
0
–Use f
0
with curve titled
center frequency vs R1, C
to determine R1 and C1
–Given: f
0
and f
L
–Calculate f
min
from the
equation f
min
e
f
o
b
f
L
–Use f
min
with curve titled
offset frequency vs R2, C
to determine R2 and C1
–Calculate f
max
/f
min
from
the equation f
max
/f
min
e
f
o
a
f
L
/f
o
b
f
L
–Use f
max
/f
min
with curve
titled f
max
/f
min
vs R2/R1
to determine ratio R2/R1
to obtain R1
–Given: f
max
–Calculate f
0
from the
equation f
o
e
f
max
/2
–Use f
0
with curve titled
center frequency vs R1, C
to determine R1 and C1
–Given: f
min
and f
max
–Use f
min
with curve titled
offset frequency vs R2,
C to determine R2 and C1
–Calculate f
max
/f
min
–Use f
max
/f
min
with curve
titled f
max
/f
min
vs R2/R1
to determine ratio R2/R1
to obtain R1
(b)
FIGURE 1
(Continued)
Detailed Circuit Description
VOLTAGE CONTROLLED OSCILLATOR/SOURCE
FOLLOWER
The VCO requires two or three external components to op-
erate. These are R1, R2, C1. Resistor R1 and capacitor C1
are selected to determine the center frequency of the VCO.
R1 controls the lock range. As R1’s resistance decreases
the range of f
min
to f
max
increases. Thus the VCO’s gain
decreases. As C1 is changed the offset (if used) of R2, and
the center frequency is changed. (See typical performance
curves) R2 can be used to set the offset frequency with 0V
at VCO input. If R2 is omitted the VCO range is from 0Hz. As
R2 is decreased the offset frequency is increased. The ef-
fect of R2 is shown in the design information table and typi-
cal performance curves. By increasing the value of R2 the
lock range of the PLL is offset above 0Hz and the gain
(Volts/rad.) does not change. In general, when offset is de-
sired, R2 and C1 should be chosen first, and then R1 should
be chosen to obtain the proper center frequency.
Internally the resistors set a current in a current mirror as
shown in Figure 1. The mirrored current drives one side of
TL/F/11675–18
FIGURE 2. Logic Diagram for VCO
8
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| 74VHC4052 | Analog Multiplexers/Demultiplexers |
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| 74VHC4052N | Dual 2-Line To 4-Line Decoders/Demultiplexers 16-SOIC -40 to 85 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 74VHC4046MTCX_NL | 功能描述:锁相环 - PLL FINISHED GOOD RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| 74VHC4046MX | 功能描述:锁相环 - PLL CMOS Phase-Lock Loop RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| 74VHC4046N | 功能描述:锁相环 - PLL CMOS Phase-Lock Loop RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| 74VHC4046NX | 制造商:NSC 制造商全称:National Semiconductor 功能描述:CMOS Phase Lock Loop |
| 74VHC4051 | 制造商:FAIRCHILD 制造商全称:Fairchild Semiconductor 功能描述:8-Channel Analog Multiplexer . Dual 4-Channel Analog Multiplexer . Triple 2-Channel Analog Multiplexer |
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