参数资料
型号: 74VHC4046NX
厂商: National Semiconductor Corporation
英文描述: CMOS Phase Lock Loop
中文描述: 的CMOS锁相环
文件页数: 9/14页
文件大小: 283K
代理商: 74VHC4046NX
Detailed Circuit Description
(Continued)
the capacitor once the capacitor charges up to the thresh-
old of the schmitt trigger the oscillator logic flips the capaci-
tor over and causes the mirror to charge the opposite side
of the capacitor. The output from the internal logic is then
taken to pin 4.
The input to the VCO is a very high impedance CMOS input
and so it will not load down the loop filter, easing the filters
design. In order to make signals at the VCO input accessible
without degrading the loop performance a source follower
transistor is provided. This transistor can be used by con-
necting a resistor to ground and its drain output will follow
the VCO input signal.
An inhibit signal is provided to allow disabling of the VCO
and the source follower. This is useful if the internal VCO is
not being used. A logic high on inhibit disables the VCO and
source follower.
The output of the VCO is a standard high speed CMOS
output with an equivalent LSTTL fanout of 10. The VCO
output is approximately a square wave. This output can ei-
ther directly feed the comparator input of the phase compar-
ators or feed external prescalers (counters) to enable fre-
quency synthesis.
PHASE COMPARATORS
All three phase comparators share two inputs, Signal In and
Comparator In. The Signal In has a special DC bias network
that enables AC coupling of input signals. If the signals are
not AC coupled then this input requires logic levels the
same as standard 74VHC. The Comparator input is a stan-
dard digital input. Both input structures are shown in Figure
3.
The outputs of these comparators are essentially standard
74VHC voltage outputs. (Comparator II is TRI-STATE.)
TL/F/11675-19
FIGURE 3. Logic Diagram for Phase Comparator I and the Common Input Circuit for All Three Comparators
TL/F/11675–20
FIGURE 4. Typical Phase Comparator I. Waveforms
9
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