参数资料
型号: 74VHCT374ASJX
厂商: Fairchild Semiconductor
文件页数: 5/9页
文件大小: 0K
描述: IC FLIP FLOP OCT D 2ST 20SOP
标准包装: 2,000
系列: 74VHCT
功能: 标准
类型: D 型总线
输出类型: 三态非反相
元件数: 1
每个元件的位元数: 8
频率 - 时钟: 130MHz
延迟时间 - 传输: 5.6ns
触发器类型: 正边沿
输出电流高,低: 8mA,8mA
电源电压: 4.5 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-SOIC(0.209",5.30mm 宽)
包装: 带卷 (TR)
74VHCT374A
Octal
D-T
ype
Flip-Flop
with
3-ST
A
TE
Outputs
1997 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74VHCT374A Rev. 1.3
5
AC Electrical Characteristics
Notes:
7. Parameter guaranteed by design. tOSLH = |tPLH max – tPLH min|; tOSHL = |tPHL max – tPHL min|
8. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load. Average operating current can be obtained by the equation:
ICC (Opr.) = CPD VCC fIN + ICC / 8 (per F/F). The total CPD when n pcs. of the octal D Flip-Flop operates
can be calculated by the equation: CPD(total) = 20 + 12m
AC Operating Requirements
Symbol
Parameter
VCC (V)
Conditions
TA = 25°C
TA = –40°C
to +85°C
Units
Min.
Typ. Max. Min.
Max.
tPLH, tPHL
Propagation Delay
Time
5.0 ± 0.5
CL = 15pF
4.1
9.4
1.0
10.5
ns
CL = 50pF
5.6
10.4
1.0
11.5
tPZL, tPZH
3-STATE Output
Enable Time
5.0 ± 0.5
RL = 1k CL = 15pF
6.5
10.2
1.0
11.5
ns
CL = 50pF
7.3
11.2
1.0
12.5
tPLZ, tPHZ
3-STATE Output
Disable Time
5.0 ± 0.5
RL = 1k CL = 50pF
7.0
11.2
1.0
12.0
ns
tOSLH, tOSHL Output to Output
Skew
5.0 ± 0.5 (7)
1.0
ns
fMAX
Maximum Clock
Frequency
5.0 ± 0.5
CL = 15pF
90
140
80
MHz
CL = 50pF
85
130
75
CIN
Input Capacitance
VCC = Open
4
10
pF
COUT
Output Capacitance
VCC = 5.0V
9
pF
CPD
Power Dissipation
Capacitance
(8)
25
pF
Symbol
Parameter
VCC (V)
TA = 25°C
TA = –40°C to +85°C
Units
Min.
Typ.
Max.
Min.
Max.
tW(H), tW(L) Minimum Pulse Width (CP)
5.0 ± 0.5
6.5
8.5
ns
tS
Minimum Set-up Time
5.0 ± 0.5
2.5
ns
tH
Minimum Hold Time
5.0 ± 0.5
2.5
ns
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