7534 Group
Rev.2.00 Jun 21, 2004 page 44 of 54
REJ03B0099-0200Z
Timing Requirements
Table 12 Timing requirements (V
CC
= 4.1 to 5.5 V, V
SS
= 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Min.
15
166
70
70
200
80
80
1000
400
400
200
200
Typ.
Max.
Symbol
Parameter
Limits
Unit
t
W
(RESET)
t
C
(X
IN
)
t
WH
(X
IN
)
t
WL
(X
IN
)
t
C
(CNTR)
t
WH
(CNTR)
t
WL
(CNTR)
t
C
(S
CLK
)
t
WH
(S
CLK
)
t
WL
(S
CLK
)
t
su
(S
DATA
–S
CLK
)
t
h
(S
CLK
–S
DATA
)
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR
0
input cycle time
CNTR
0
, INT
0
, INT
1
input “H” pulse width
CNTR
0
, INT
0
, INT
1
input “L” pulse width
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 input set up time
Serial I/O2 input hold time
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Switching Characteristics
Table 13 Switching characteristics (V
CC
= 4.1 to 5.5 V, V
SS
= 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Min.
Typ.
Max.
Symbol
Parameter
Limits
Unit
t
WH
(S
CLK
)
t
WL
(S
CLK
)
t
d
(S
CLK
–S
DATA
)
t
v
(S
CLK
–S
DATA
)
t
r
(S
CLK
)
t
f
(S
CLK
)
t
r
(CMOS)
t
f
(CMOS)
t
r
(D+), t
r
(D-)
t
f
(D+), t
f
(D-)
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output rising time
Serial I/O2 clock output falling time
CMOS output rising time (Note)
CMOS output falling time (Note)
USB output rising time, C
L
= 200 to 450 pF, Ta = 0 to 70 °C, V
CC
=
4.4 to 5.25 V
USB output falling time, C
L
= 200 to 450 pF, Ta = 0 to 70 °C, V
CC
=
4.4 to 5.25 V
Notes:
X
OUT
pin is excluded.
10
10
150
150
75
75
Fig. 49 Output switching characteristics measurement circuit
100 pF
Measured
output pin
CMOS output
t
C
(S
CLK
)/2–30
t
C
(S
CLK
)/2–30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
140
30
30
30
30
300
300