参数资料
型号: 78M6610+PSU/C00T
厂商: Maxim Integrated
文件页数: 6/63页
文件大小: 0K
描述: IC ENERGY MEASURMENT 1PH 16TSSOP
标准包装: 2,500
输入阻抗: 30 千欧 ~ 90 千欧
电压 - 高输入/输出: 2V
电压 - 低输入/输出: 0.8V
电流 - 电源: 8.1mA
电源电压: 3 V ~ 3.6 V
测量仪表类型: 单相
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 16-TSSOP
包装: 带卷 (TR)
78M6610+PSU Data Sheet
1.2
Power-On Reset, WD Timer, and Reset Circuitry
events in noisy environments. The reset does not occur until RESET has been held low for at least 1 μs.
Power-On Reset (POR)
An on-chip Power-On Reset (POR) block monitors the supply voltage (V 3P3D ) and initializes the internal
digital circuitry at power-on. Once V 3P3D is above the minimum operating threshold, the POR circuit
triggers and initiates a reset sequence. It will also issue a reset to the digital circuitry if the supply voltage
falls below the minimum operating level.
Watchdog Timer (WDT)
A Watchdog Timer (WDT) block detects any software processing errors. The embedded software
periodically refreshes the free-running watchdog timer to prevent it from timing out. If the WDT times out,
it is an indication that software is no longer being executed in the intended sequence; thus, a system
reset is initiated.
External Reset Pin ( RESET Pin)
The 24-pin QFN package provides a dedicated reset ( RESET ) pin. In addition to the internal sources, a
reset can be forced by applying a low level to the RESET pin.
If the RESET pin is pulled low, all digital activities in the device stop, except the clock management
circuitry and oscillators, which continue to run. The external reset input is filtered to prevent spurious reset
Once initiated, the reset mode persists until the RESET is set high and the reset timer times out (4096
clock cycles). At the completion of the reset sequence, the internal reset is released and the processor
(EMP) begins executing from address 0.
If not used, the RESET pin can be connected either directly or through a pull-up resistor to V 3P3D supply.
A simple connection diagram is shown in Figure 3.
V 3P3D
V 3P3
V 3P3D
V 3P3
10K Ω
RESET
GNDD
1nF
Manual
Reset Switch
RESET
GNDD
78M6610+PSU/B
GND
78M6610+PSU/B
GND
a) RESET External Connection Example
b) Unused RESET Connection Example
Figure 3: RESET Pin Connections
6
Rev 1
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