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| 型号： | 78M6618-SOCKET68 |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 11/32页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD 78M6618 68PIN QFN |
| 标准包装： | 1 |
| 系列： | * |
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DS_6618_005
78M6618 Data Sheet
1.16 LCD Drivers
The 78M6618 contains a total of 35 dedicated and multiplexed LCD drivers which are grouped as follows:
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11 dedicated LCD segment drivers.
3 drivers multiplexed with the ICE interface (E_TCLK, E_RST, E_RXTX).
1 driver multiplexed with auxiliary signal CKTEST (SEG19).
4 drivers multiplexed with the SPI port (PCLK, PSDO, PCSZ, PSDI).
16 drivers multiplexed with general purpose DIO pins.
2 common drivers for multiplexing (50%, or 100% duty cycle) – always available.
With a minimum of 15 driver pins always available and a total of 35 driver pins in the maximum con-
figuration, the device is capable of driving between 30 to 70 pixels of LCD display. At eight pixels per digit,
this corresponds to 3 to 8 digits. The following dedicated and multi-use pins can be assigned as LCD
segment pins for the 78M6618:
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11 dedicated LCD segment pins: SEG0 to SEG2, SEG7, SEG8, SEG12, SEG14 to SEG18.
8 dual-function pins: SEG3/PCLK, SEG4/PSDO, SEG5/PCSZ, SEG6/PSDI, E_RXTX/SEG9,
E_TCLK/SEG10, E_RST/SEG11, and SEG19/CKTEST.
16 combined DIO and segment pins: SEG24/DIO4 to SEG31/DIO11, SEG33/DIO13 to
SEG39/DIO19, and SEG63/DIO43. Of which, DIO7/SEG27 through DIO15/SEG35 can be used for
controlling relays.
See the 78M6618 Programmer’s Reference Manual for more information regarding the programmability
of the 78M6618 LCD drivers. See the 78M6618 Hardware Design Guidelines for more information
regarding connecting the 78M6618 LCD drivers to LCDs.
1.17 EEPROM Interface
The 78M6618 provides hardware support for an optional two-pin or a three-wire ( μ -wire) EEPROM
interface.
Two-Pin EEPROM Interface
The dedicated 2-pin serial interface communicates with external EEPROM devices. The interface is
multiplexed onto the DIO4 (SCK) and DIO5 (SDA) pins.
Three-Wire ( μ -Wire) EEPROM Interface
A 500 kHz three-wire interface, using SDATA, SCK and a DIO pin for CS is also available.
See the 78M6618 Programmer’s Reference Manual for more information regarding the programmability
of the 78M6618 EEPROM interfaces. See the 78M6618 Hardware Design Guidelines for more
information regarding connecting the 78M6618 EEPROM interfaces to various EEPROM.
1.18 SPI Slave Port
The slave SPI port communicates directly with the MPU data bus and is able to directly read and write
XRAM and IORAM locations. It is also able to send commands to the MPU. The interface to the slave
port consists of the PCSZ, PCLK, PSDI and PSDO pins. These pins are multiplexed with the LCD
segment driver pins SEG3 to SEG6.
A typical SPI transaction is as follows. While PCSZ is high, the port is held in an initialized/reset state.
During this state, PSDO is held in HiZ state and all transitions on PCLK and PSDI are ignored. When
PCSZ falls, the port will begin the transaction on the first rising edge of PCLK. A transaction consists of
an 8-bit command, a 16-bit address and then one or more bytes of data. The transaction ends when
PCSZ is raised. Some transactions may consist of a command only. The last SPI command and address
(if part of the command) are available in the IORAM.
Rev. 1.4
11
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