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参数资料
| 型号： | 78P7200L |
| 厂商： | TDK Corporation |
| 英文描述： | E3/DS3/STS-1 Transceiver |
| 中文描述： | E3/DS3/STS-1收发器 |
| 文件页数： | 2/11页 |
| 文件大小： | 171K |
| 代理商： | 78P7200L |
78P7200
E3/DS3/STS-1
Line Interface Unit
FUNCTIONAL DESCRIPTION
The 78P7200 is a single chip line interface IC
designed to work with either a 51.84 Mbit/s STS-1,
44.736 Mbit/s DS3 or 34.368 Mbit/s E3 signal. The
receiver recovers clock, positive data and negative
data from an Alternate Mark Inversion (AMI) signal.
The input signal should be B3ZS or HDB3 coded.
The transmitter accepts CMOS level logical clock,
positive data and negative data and converts them
to the AMI signal to drive a 75
coaxial cable.
Programmable internal Line Buildout (LBO) circuitry
eliminates the need for external LBO networks.
When the option pins are properly selected, the
shape of the transmitted signal through any cable
length of 0 to 450 feet complies with the published
templates of ANSI T1.102, ITU-T G.703, Bellcore
TR-NWT-000499 and GR-253-CORE. The 78P7200
is designed to work with a B3ZS or HDB3 coded
signal. The B3ZS or HDB3 encoding and decoding
functions are normally included in the framer ICs or
can easily be implemented in a PAL.
RECEIVER
The receiver input is normally transformer-coupled to
the AMI signal. The inputs to the IC are internally
referenced to RVCC. Since the input impedance of
the 78P7200 is high, the AMI line must be
terminated in 75
. The input signal to the 78P7200
must be limited to a maximum of three consecutive
zeros using a coding scheme such as B3ZS or
HDB3.
The AMI signal first enters a fixed equalizer, which is
designed to overcome the intersymbol interference
caused by long cable lengths and crosstalk. This
fixed equalizer is optimized for DS3 application and
its effect should be compensated by an external filter
circuit similar to Figure 1, for all square shaped
signals such as DS3-high or 34 Mbit/s E3. For all
new designs, the addition of the filter for DS3 and
STS-1 as well as E3 rate allows the circuit to work
with sharp pulses such as DS3-high. The signal is
then input to a variable gain differential amplifier
whose output is maintained at a constant voltage
level regardless of the input voltage level. The gain
of this amplifier is adjusted by detecting the peak of
the signal and comparing it to a fixed reference.
Page: 2 of 11
2005 Teridian Semiconductor Corporation
Rev 3.0
The output of the variable gain amplifier is compared
to a threshold value, which is a fixed percentage of
the signal peak. In this way, even though the input
signal amplitude may fall below the minimum value
that can be regulated by the variable gain circuit, the
proper detection threshold is maintained.
Outputs of the data comparators are connected to
the clock recovery circuits. The clock recovery
system employs a unique phase locked loop, which
has an auxiliary frequency-sensitive acquisition loop,
which becomes active only when cycle-slipping
occurs between the received signal rate and the
internal oscillator.
This system permits the loop to independently lock
to the frequency and phase of the incoming data
stream without the need for high precision and/or
adjustable oscillator or tuned circuits.
The frequency characteristic for the phase locked
loop is established by external filter components,
RLF1, RLF2 and CLF1. The values of these
components are specified such that the bandwidth of
the phase locked loop is greater than 200 kHz.
The jitter tolerance of the 78P7200 exceeds the
requirements of TR-NWT-000499 for Category II
equipment
for
DS3
rate
requirements of ITU-T G.823 for E3 rate. The jitter
transfer function is maximally flat so the IC doesn't
add any significant jitter to the system.
Figure 2 shows the recovered clock (RCLK), positive
data (RPOS) and negative data (RNEG) signals
timing. The data is valid on the rising edge of the
clock. The minimum setup and hold times allow easy
interface to framer circuits. These signals are
CMOS-level outputs.
Should the input signal fall below a minimum value,
the
LOWSIG
pin goes active low. A time delay is
provided before this output is active so that transient
interruptions do not cause false indications. This
signal should be used as one of many indications to
the cable disconnect; the framer device should count
the number of zeros to declare the loss of signal.
The RPOS and RNEG signals generate random
data following a silence period. The framer device
should ignore RPOS and RNEG data if the
LOWSIG
pin is active low.
and
exceeds
the
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 78P7200LIGT | 制造商:TDK 功能描述: |
| 78P7200L-IGT | 制造商:Maxim from Components Direct 功能描述:MAXIM 78P7200L-IGT FRAMERS - Trays 制造商:Maxim 功能描述:Maxim 78P7200L-IGT Framers |
| 78P7200L-IGT/F | 制造商:Maxim Integrated Products 功能描述: |
| 78P7200L-IH | 制造商:Maxim Integrated Products 功能描述: |
| 78P7200L-IH/F | 制造商:Maxim Integrated Products 功能描述:MAXIM 78P7200L-IH/F LINE INTERFACE UNITS - Rail/Tube 制造商:Maxim Integrated Products 功能描述:Maxim 78P7200L-IH/F Line Interface Units |
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