参数资料
型号: 83PN625DKILF
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: XO, clock
英文描述: 625 MHz, OTHER CLOCK GENERATOR, QCC10
封装: 5 X 7 MM, 1 MM PITCH, ROHS COMPLIANT, VFQFN-10
文件页数: 2/17页
文件大小: 1314K
代理商: 83PN625DKILF
ICS83PN625I Data Sheet
PROGRAMMABLE FEMTOCLOCK NG LVPECL OSCILLATOR REPLACEMENT
ICS83PN625DKI REVISION A MARCH 17, 2010
10
2010 Integrated Device Technology, Inc.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential output is low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
Figure 4A. 3.3V LVPECL Output Termination
Figure 4B. 3.3V LVPECL Output Termination
3.3V
V
CC - 2V
R1
50
R2
50
RTT
Z
o = 50
Z
o = 50
+
_
RTT =
* Z
o
1
((V
OH + VOL) / (VCC – 2)) – 2
3.3V
LVPECL
Input
R1
84
R2
84
3.3V
R3
125
R4
125
Z
o = 50
Z
o = 50
LVPECL
Input
3.3V
+
_
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