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| 型号： | 844031AG-01LFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 340 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| 封装： | 4.40 X 3 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-8 |
| 文件页数： | 12/13页 |
| 文件大小： | 278K |
| 代理商： | 844031AG-01LFT |
IDT / ICS LVDS CLOCK GENERATOR
8
ICS844031BG-01 REV. A MAY 1, 2008
ICS844031-01
FEMTOCLOCKS CRYSTAL-TO-LVDS CLOCK GENERATOR
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in
Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise. This configuration requires that the output
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50
Ω applications, R1
and R2 can be 100
Ω.This can also be accomplished by removing
R1 and making R2 50
Ω.
R2
Zo = 50
VDD
Ro
Zo = Ro + Rs
R1
VDD
XTAL_IN
XTAL_OUT
.1uf
Rs
3.3V, 2.5V LVDS DRIVER TERMINATION
A general LVDS interface is shown in
Figure 4 In a 100
Ω
differential transmission line environment, LVDS drivers
require a matched load termination of 100
Ω across near
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
the receiver input. For a multiple LVDS outputs buffer, if only
partial outputs are used, it is recommended to terminate the
unused outputs.
R1
100
3.3V or 2.5V
100
Ω Differential Transmission
VDD
+
-
LVDS
相关PDF资料 |
PDF描述 |
|---|---|
| 844031AG-01LF | 340 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| 84450-1 | 50 CONTACT(S), MALE, RIGHT ANGLE TWO PART BOARD CONNECTOR, SOLDER |
| 84476-1 | 4 CONTACT(S), MALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT |
| 84476-2 | 6 CONTACT(S), MALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT |
| 84476-3 | 16 CONTACT(S), MALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 844031BG-01LF | 功能描述:时钟发生器及支持产品 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| 844031BG-01LFT | 功能描述:时钟发生器及支持产品 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| 844031BGI-01 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Generator Single 8-Pin TSSOP Tube 制造商:Integrated Device Technology Inc 功能描述:8 TSSOP - Bulk |
| 844031BGI-01LF | 功能描述:时钟发生器及支持产品 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| 844031BGI-01LFT | 功能描述:时钟发生器及支持产品 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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