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参数资料
| 型号： | 873034AMLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 873034 SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封装： | 7.50 X 10.30 MM, 2.30 MM HEIGHT, ROHS COMPLIANT, MS-012, SOIC-16 |
| 文件页数： | 15/16页 |
| 文件大小： | 298K |
| 代理商： | 873034AMLFT |
873034AM
8
REV. A JANUARY 17, 2008
ICS873034
LOW SKEW, ÷2, ÷4, ÷8 DIFFERENTIAL-TO-
2.5V, 3.3V LVPECL/ECL CLOCK GENERATOR
PRELIMINARY
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both V
SWING and VOH must meet the VPP
and V
CMR input requirements. Figures 3A to 3F show inter-
face examples for the HiPerClockS PCLK/nPCLK input driven
by the most common driver types. The input interfaces sug-
gested here are examples only. If the driver is from another
vendor, use their termination recommendation. Please con-
sult with the vendor of the driver component to confirm the
driver termination requirements.
FIGURE 3A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN
OPEN COLLECTOR CML DRIVER
FIGURE 3B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A
BUILT-IN PULLUP CML DRIVER
FIGURE 3C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A
3.3V LVPECL DRIVER
FIGURE 3F.
HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A
3.3V LVDS DRIVER
PCLK/nPCLK
2.5V
Zo = 60 Ohm
SSTL
HiPerClockS
PCLK
nPCLK
R2
120
3.3V
R3
120
Zo = 60 Ohm
R1
120
R4
120
2.5V
FIGURE 3E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN
SSTL DRIVER
HiPerClockS
PCLK
nPCLK
PCLK/nPCLK
3.3V
R2
50
R1
50
3.3V
Zo = 50 Ohm
CML
3.3V
Zo = 50 Ohm
3.3V
HiPerClockS
PCLK
nPCLK
R2
84
R3
125
Input
Zo = 50 Ohm
R4
125
R1
84
LVPECL
3.3V
Zo = 50 Ohm
FIGURE 3D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A
3.3V LVPECL DRIVER WITH AC COUPLE
3.3V
CML Built-In Pullup
R1
100
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
Zo = 50 Ohm
R2
50
Zo = 50 Ohm
C1
R1
50
C2
PC L K/n PC L K
R5
100 - 200
Zo = 50 Ohm
R6
100 - 200
PCLK
nPCLK
VBB
3.3V LVPECL
3.3V
LVDS
3.3V
Zo = 50 Ohm
3.3V
PCLK
nPCLK
VBB
R2
1K
C2
R1
1K
R5
100
C1
PC L K /n PC L K
Zo = 50 Ohm
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相关代理商/技术参数 |
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