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参数资料
| 型号： | 8904 |
| 厂商： | Allegro MicroSystems, Inc. |
| 英文描述： | 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER WITH BACK-EMF SENSING |
| 中文描述： | 3相无刷直流电动机控制器/驱动器，反电动势遥感 |
| 文件页数： | 4/18页 |
| 文件大小： | 744K |
| 代理商： | 8904 |
8904
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
4
ELECTRICAL CHARACTERISTICS at T
A
= +25°C, V
DD
= 5.0 V
Limits
Characteristic
Logic Supply Voltage
Logic Supply Current
Symbol
V
DD
I
DD
Test Conditions
Min.
4.5
—
—
—
—
4.0
—
—
—
—
Typ.
5.0
7.5
250
3.6
3.9
—
4.0
20
165
20
Max.
5.5
10
500
—
—
14
8.0
30
—
—
Units
V
mA
μA
V
V
V
mA
μA
°C
°C
Operating
Operating
Sleep mode
Decreasing V
DD
Increasing V
DD
Operating
Operating
Sleep mode
Undervoltage Threshold
UVLO
Load Supply Voltage
Load Supply Current
V
BB
I
BB
Thermal Shutdown
Thermal Shutdown Hysteresis
Output Drivers
Output Leakage Current
T
J
T
J
I
DSX
V
BB
= 14 V, V
OUT
= 14 V, sleep mode
V
BB
= 14 V, V
OUT
= 0 V
I
OUT
= 600 mA
—
—
—
200
-2.0
1.0
300
-15
1.4
μA
μA
Total Output ON Resistance
(source + sink + R
S
)
Output Sustaining Voltage
Clamp Diode Forward Voltage
Control Logic
Logic Input Voltage
r
DS(on)
V
DS(sus)
V
F
V
BB
= 14 V, I
OUT
= I
OUT
(MAX), L = 3 mH
I
F
= 1.0 A
14
—
—
1.25
—
1.5
V
V
V
IN(0)
V
IN(1)
I
IN(0)
I
IN(1)
V
BRK
I
BRKL
I
BRK
V
OUT(0)
V
OUT(1)
I
CST
SECTOR DATA, RESET, CLK,
CHIP SELECT, OSC
V
IN
= 0 V
V
IN
= 5.0 V
—
2.0
—
—
1.5
—
—
—
3.5
-9.0
—
2.25
0.85
-9.0
9.0
—
1.57
-18
32
1.8
2.25
—
—
—
—
—
1.75
4.0
20
—
—
-10
500
2.5
1.0
-10
10
—
1.85
-20
40
2.0
2.5
—
0.8
—
-0.5
±1.0
2.0
—
—
1.5
—
-11
—
2.75
1.15
-11
11
±5.0
2.13
-22
48
2.2
2.75
1.0
V
V
μA
μA
V
μA
μA
V
V
μA
μA
V
V
μA
μA
nA
V
μA
μA
—
V
μA
Logic Input Current
BRAKE Threshold
BRAKE Hysteresis Current
BRAKE Current
DATA Output Voltage
V
BRK
= 750 mV
Brake set, D2 = 1, I
BRK
= 750 mV
I
OUT
= 500 μA
I
OUT
= -500 μA
Charging
Discharging, V
CST
= 2.5 V
High
Low
Charging
Discharging
Leakage, V
FILTER
= 2.5 V
C
ST
Current
C
ST
Threshold
V
CSTH
V
CSTL
I
FILTER
Filter Current
Filter Threshold
C
D
Current
(C
D1
or C
D2
)
V
FILTERTH
I
CD
Charging
Discharging
I
CD(DISCHRG)
/I
CD(CHRG)
C
D
Current Matching
C
D
Threshold
C
D
Input Leakage
—
V
CDTH
I
CDIL
Continued next page …
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