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参数资料
| 型号： | 89HPES12T3G2ZABCG |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 总线控制器 |
| 英文描述： | 12-Lane 3-Port Gen2 PCI Express Switch |
| 中文描述： | PCI BUS CONTROLLER, PBGA324 |
| 封装： | 19 X 19 MM, 1 MM PITCH, GREEN, CABGA-324 |
| 文件页数： | 4/31页 |
| 文件大小： | 291K |
| 代理商： | 89HPES12T3G2ZABCG |
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September 4, 2007
IDT 89HPES12T3G2 Data Sheet
A
Pin Desc ription
The following tables list the functions of the pins provided on the PES12T3G2. Some of the functions listed may be multiplexed onto the same pin.
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Note:
In the PES12T3G2, the two downstreamports are labeled port 2 and port 4.
S ignal
Type
Name/Desc ription
PE0RP[3:0]
PE0RN[3:0]
I
PCI Express Port 0 Serial Data Receive.
Differential PCI Express receive
pairs for port 0. Port 0 is the upstreamport.
PE0TP[3:0]
PE0TN[3:0]
O
PCI Express Port 0 Serial Data Transmit.
Differential PCI Express trans-
mt pairs for port 0. Port 0 is the upstreamport.
PE2RP[3:0]
PE2RN[3:0]
I
PCI Express Port 2 Serial Data Receive.
Differential PCI Express receive
pairs for port 2.
PE2TP[3:0]
PE2TN[3:0]
O
PCI Express Port 2 Serial Data Transmit.
Differential PCI Express trans-
mt pairs for port 2.
PE4RP[3:0]
PE4RN[3:0]
I
PCI Express Port 4 Serial Data Receive.
Differential PCI Express receive
pairs for port 4.
PE4TP[3:0]
PE4TN[3:0]
O
PCI Express Port 4 Serial Data Transmit.
Differential PCI Express trans-
mt pairs for port 4.
PEREFCLKP[0]
PEREFCLKN[0]
I
PCI Express Reference Clock.
Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the systemlogic and on-chip SerDes. The frequency of the dif-
ferential reference clock is determned by the REFCLKMsignal.
REFCLKM
I
PCI Express Reference Clock Mode Select.
This signal selects the fre-
quency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
This pin should be static and not change following the negation of
PERSTN.
Table 2 PCI Express Interface Pins
S ignal
Type
Name/Desc ription
MSMBADDR[4:1]
I
Master SMBus Address.
These pins determne the SMBus address of the
serial EEPROMfromwhich configuration information is loaded.
MSMBCLK
I/O
Master SMBus Clock.
This bidirectional signal is used to synchronize
transfers on the master SMBus.
MSMBDAT
I/O
Master SMBus Data.
This bidirectional signal is used for data on the mas-
ter SMBus.
SSMBADDR[5,3:1]
I
Slave SMBus Address.
These pins determne the SMBus address to
which the slave SMBus interface responds.
SSMBCLK
I/O
Slave SMBus Clock.
This bidirectional signal is used to synchronize trans-
fers on the slave SMBus.
SSMBDAT
I/O
Slave SMBus Data.
This bidirectional signal is used for data on the slave
SMBus.
Table 3 SMBus Interface Pins
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 89HPES12T3G2ZABCG8 | 功能描述:开关 IC - 各种 RoHS:否 制造商:Fairchild Semiconductor 开启电阻（最大值）: 电源电压-最大:4.4 V 电源电压-最小:2.5 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:WLCSP-9 封装:Reel |
| 89HPES12T3G2ZBBC | 功能描述:Switch Interfacing Interface 324-CABGA (19x19) 制造商:idt, integrated device technology inc 系列:PRECISE?? 包装:托盘 零件状态:有效 应用:开关接口 接口:PCI Express 电压 - 电源:3.3V 封装/外壳:324-LBGA 供应商器件封装:324-CABGA（19x19） 安装类型:表面贴装 标准包装:84 |
| 89HPES12T3G2ZBBC8 | 功能描述:开关 IC - 各种 RoHS:否 制造商:Fairchild Semiconductor 开启电阻（最大值）: 电源电压-最大:4.4 V 电源电压-最小:2.5 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:WLCSP-9 封装:Reel |
| 89HPES12T3G2ZBBCG | 功能描述:开关 IC - 各种 RoHS:否 制造商:Fairchild Semiconductor 开启电阻（最大值）: 电源电压-最大:4.4 V 电源电压-最小:2.5 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:WLCSP-9 封装:Reel |
| 89HPES12T3G2ZBBCG8 | 功能描述:接口-I/O扩展器 RoHS:否 制造商:NXP Semiconductors 逻辑系列: 输入/输出端数量: 最大工作频率:100 kHz 工作电源电压:1.65 V to 5.5 V 工作温度范围:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体:HVQFN-16 封装:Reel |
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