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参数资料
| 型号： | 9084901MCA |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 锁存器 |
| 英文描述： | HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14 |
| 封装： | HERMETIC SEALED, CERAMIC, DIP-14 |
| 文件页数： | 13/16页 |
| 文件大小： | 458K |
| 代理商： | 9084901MCA |
6
Power Dissipation Capacitance
(Notes 3, 4)
CPD
-
5
-
31
-
----
pF
HCT TYPES
Propagation Delay,
CP to Q
tPLH, tPHL
CL = 50pF
4.5
-
43
-
54
-
65
ns
CL = 15pF
5
-
18
-
----
ns
Propagation Delay,
CP to Q
tPLH, tPHL
CL = 50pF
4.5
-
40
-
50
-
60
ns
CL = 15pF
5
-
17
-
----
ns
Propagation Delay,
R to Q, Q
tPLH, tPHL
CL = 50pF
4.5
-
38
-
48
-
57
ns
CL = 15pF
5
-
16
-
----
ns
Output Transition Time
tTLH, tTHL
CL = 50pF
4.5
-
15
-
19
-
22
ns
Input Capacitance
CI
-
10
-
10
-
10
pF
CP Frequency
fMAX
CL = 15pF
5
-
56
-
----
MHz
Power Dissipation Capacitance
(Notes 3, 4)
CPD
-
5
-
30
-
----
pF
NOTES:
3. CPD is used to determine the dynamic power consumption, per flip-flop.
4. PD =CPD VCC
2 f
i + Σ CL VCC
2 f
o where fi = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage.
Switching Specications Input tr, tf = 6ns (Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
VCC
(V)
25oC
-40oC TO 85oC
-55oC TO 125oC
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
Test Circuits and Waveforms
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
CLOCK
90%
50%
10%
GND
VCC
trCL
tfCL
50%
tWL
tWH
10%
tWL + tWH =
fCL
I
CLOCK
2.7V
1.3V
0.3V
GND
3V
trCL = 6ns
tfCL = 6ns
1.3V
tWL
tWH
0.3V
tWL + tWH =
fCL
I
tPHL
tPLH
tTHL
tTLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
VCC
tr = 6ns
tf = 6ns
90%
tPHL
tPLH
tTHL
tTLH
2.7V
1.3V
0.3V
1.3V
10%
INVERTING
OUTPUT
INPUT
GND
3V
tr = 6ns
tf = 6ns
90%
CD54HC107, CD74HC107, CD74HCT107
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