参数资料
型号: 9112AM-17T
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟及定时
英文描述: 9112 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
封装: 0.150 INCH, MS-012, SOIC-16
文件页数: 8/12页
文件大小: 163K
代理商: 9112AM-17T
5
ICS9112-17
0051J—02/05/04
Output to Output Skew
The skew between CLKOUT and the CLKA/B outputs is not dynamically adjusted by the PLL. Since CLKOUT is one
of the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded,
zero phase difference will maintained from REF to all outputs.
If applications requiring zero output-output skew, all the outputs must equally loaded.
If the CLKA/B outputs are less loaded than CLKOUT, CLKA/B outputs will lead it; and if the CLKA/B is more loaded
than CLKOUT, CLKA/B will lag the CLKOUT.
Since the CLKOUT and the CLKA/B outputs are identical, they all start at the same time, but different loads cause them
to have different rise times and different times crossing the measurement thresholds.
REF input and
all outputs
loaded Equally
REF input and CLKA/B
outputs loaded equally, with
CLKOUT loaded More.
REF input and CLKA/B
outputs loaded equally, with
CLKOUT loaded Less.
Timing diagrams with different loading configurations
相关PDF资料
PDF描述
9112AF-17LFT 9112 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
9112AM-17LF 9112 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
9112AF-17 9112 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
9112AF-17T 9112 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
9112BM-17LF-T 9112 SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
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