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参数资料
| 型号： | 91305AMI |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 91305 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封装： | 0.150 INCH, LEAD FREE, SOIC-8 |
| 文件页数： | 8/9页 |
| 文件大小： | 157K |
| 代理商： | 91305AMI |
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91305 (Zero Delay Buffers)
Description
The ICS91305 is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and
frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating at
speeds from 10 to 133 MHz. ICS91305 is a zero delay buffer that provides synchronization between the input and output. The synchronization is
established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than +/- 350 pS, the part acts as
a zero delay buffer. The ICS91305 comes in an eight pin 150 mil SOIC package. It has five output clocks. In the absence of REF input, will be in
the power down mode. In this mode, the PLL is turned off and the output buffers are pulled low. Power down mode provides the lowest power
consumption for a standby condition.
Market Group
PC CLOCK
Additional Info
Zero input - output delay Frequency range 10 - 133 MHz (3.3V) 5V tolerant input REF High loop filter bandwidth ideal for Spread Spectrum
applications. Less than 200 ps Jitter between outputs Skew controlled outputs Skew less than 250 ps between outputs Available in 8 pin
150 mil SOIC & 173 mil TSSOP packages 3.3V ±10% operation
[?] Home > Products > Timing Solutions > PC-Notebook-Server Clocks > DDR I and DDR II Buffers > Zero Delay Buffers > 91305
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| 91305AGLF | 91305 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
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| 91305YGI-T | 91305 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
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