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参数资料
| 型号： | 9169CM-23LF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 83.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封装： | 0.300 INCH, ROHS COMPLIANT, MS-013, MO-119, SOIC-28 |
| 文件页数： | 3/9页 |
| 文件大小： | 207K |
| 代理商： | 9169CM-23LF |
3
ICS9169C-23
Shared Pin Operation - Input/Output, Pins 5, 28, 12 and
13 on the ICS9169C-23 serve as dual signal functions to
the device. During initial power-up, they act as input pins.
The logic level (voltage) that is present on these pins at this
time is read and stored into a 4-bit internal data latch. At the
end of Power-On reset, (see AC characteristics for timing
values), the device changes the mode of operations for these
pins to an output function. In this mode the pins produce the
specified buffered clocks to external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figs. 1 and 2 show the recommended means of implementing
this function. In Fig. 1 either one of the resistors is loaded
onto the board (selective stuffing) to configure the device’s
internal logic. Figs. 2a and b
provide a single resistor
loading option where either solder spot tabs or a physical
jumper header may be used.
These figures illustrate the optimal PCB physical layout
options. These configuration resistors are of such a large
ohmic value that they do not effect the low impedance clock
signals. The layouts have been optimized to provide as little
impedance transition to the clock signal as possible, as it
passes through the programming resistor pad(s).
Shared Pin Operation -
Input/Output Pins
The ICS9169C-23 includes a production test verification
mode of operation. This requires that the FSO and FS1 pins
be programmed to a logic high and the FS2 pin be
programmed to a logic low(see Shared Pin Operation section).
In this mode the device will output the following
frequencies.
Note: REF is the frequency of either the crystal connected
between the devices X1and X2 or, in the case of a device
being driven by an external reference clock, the frequency
of the reference (or test) clock on the device’s X1 pin.
Test Mode Operation
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Fig. 1
相关PDF资料 |
PDF描述 |
|---|---|
| 917-11 | 0 MHz - 20000 MHz, 225 deg RF/MICROWAVE COAXIAL MECHANICAL PH SHIFTER |
| 917-12 | 0 MHz - 20000 MHz, 225 deg RF/MICROWAVE COAXIAL MECHANICAL PH SHIFTER |
| 917-21 | 0 MHz - 20000 MHz, 225 deg RF/MICROWAVE COAXIAL MECHANICAL PH SHIFTER |
| 917-22 | 0 MHz - 20000 MHz, 225 deg RF/MICROWAVE COAXIAL MECHANICAL PH SHIFTER |
| 917-1 | 0 MHz - 20000 MHz, 225 deg RF/MICROWAVE COAXIAL MECHANICAL PH SHIFTER |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 9169CM-23LFT | 制造商:Integrated Device Technology Inc 功能描述:9169CM-23LFT - Tape and Reel |
| 9169M-01 | 制造商:Integrated Device Technology Inc 功能描述:PLL Frequency Generator Dual 28-Pin SOIC Tube |
| 9169M-01LF | 制造商:Integrated Device Technology Inc 功能描述:PLL Frequency Generator Dual 28-Pin SOIC Tube 制造商:Integrated Device Technology Inc 功能描述:28 SOP (LEAD FREE) - Rail/Tube |
| 9169M-01LFT | 制造商:Integrated Device Technology Inc 功能描述:PLL Frequency Generator Dual 28-Pin SOIC T/R 制造商:Integrated Device Technology Inc 功能描述:28 SOP (LEAD FREE) - Tape and Reel |
| 9169P | 制造商:ITT Interconnect Solutions 功能描述:CA3106E14S-6SF80A232 |
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