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参数资料
| 型号： | 91730YMLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 91730 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封装： | 0.150 INCH, ROHS COMPLIANT, MS-012, SOIC-8 |
| 文件页数： | 3/10页 |
| 文件大小： | 130K |
| 代理商： | 91730YMLFT |
2
ICS91730
0794E—06/04/08
Pin Descriptions
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
1
CLKIN
POWER
Input for reference clock.
2
VDD
INPUT
Power supply, nominal 3.3V
3
GND
OUTPUT
Ground pin.
4
CLKOUT
I/O
Modulated clock output.
Un-modulated 3.3V reference clock output.
Frequency select latch input. Refer to the functionality table.
6
SDATA
POWER
Data pin for SMBus circuitry, 5V tolerant.
7
SCLK
POWER
Clock pin of SMBus circuitry, 5V tolerant.
8
PD#*
POWER
Asynchronous active low input pin, with 120Kohm internal pull-up
resistor, used to power down the device. The internal clocks are
disabled and the VCO and the crystal are stopped.
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor
I/O
REF_OUT/FS_IN1*
5
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