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参数资料
| 型号： | 9179BF-03 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 9179 SERIES, LOW SKEW CLOCK DRIVER, 18 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封装： | SSOP-48 |
| 文件页数： | 3/9页 |
| 文件大小： | 276K |
| 代理商： | 9179BF-03 |
3
ICS9179B -01
VDD
This is the power supply to the internal core logic of the
device as well as the clock output buffers for
SDRAM(0:17).
This pin operates at 3.3V volts. Clocks from the listed
buffers that it supplies will have a voltage swing from
Ground to this level. For the actual guaranteed high and
low voltage levels for the Clocks, please consult the DC
parameter table in this data sheet.
GND
This is the power supply ground (common or negative)
return pin for the internal core logic and all the output
buffers.
SDRAM(0:17)
These Output Clocks are use to drive Dynamic RAM’s
and are low skew copies of the CPU Clocks. The voltage
swing of the SDRAM’s output is controlled by the supply
voltage that is applied to VDD of the device, operates at
3.3 volts.
I
2C
The SDATA and SCLOCK Inputs are use to program the
device. The clock generator is a slave-receiver device in
the I
2C protocol. It will allow read-back of the registers.
See configuration map for register functions. The I
2C
specification in Philips I
2C Peripherals Data Handbook
(1996) should be followed.
BUF_IN
Input for Fanout buffers (SDRAM 0:17).
OE
OE tristates all outputs when held low.
VDDS
This is the power supply to I
2C circuitry.
GNDS
This is the ground to I
2C circuitry.
Technical Pin Function Descriptions
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