参数资料
型号: 9212AF-13LF-IN0
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟产生/分配
英文描述: 533.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO24
封装: 0.150 INCH, GREEN, SSOP-24
文件页数: 2/8页
文件大小: 167K
代理商: 9212AF-13LF-IN0
2
ICS9212-13
0272E—04/09/03
Pin Descriptions
Pin #
Name
Type
Description
1
VDDREF
REFV
Reference voltage for refclk, to be connected to CK133
2
REFCLK
IN
Reference clock, to be connected to CK133
3
VDD1
PWR
3.3 V power supply used for PLL
4
GND1
PWR
Ground for PLL
5
GND3
PWR
Ground for control inputs
6,7
PCLK/M, SYNCLK/N
IN
Phase controller input, used to drive a phase aligner
that adjusts the phase of the busclk.
8
GND2
PWR
Ground for phase aligner
9
VDD2
PWR
3.3 V power supply used for phase aligner
10
VDDPD
REFV
Reference voltage for phase detector inputs connected
to the controller
11
BUSCLK_ STOP#
IN
Active low output enable/disable
12
PD#
IN
3.3V CMOS active low power down, the device is
powered down when the "(PD#) =0"
14,15
MULTI (0:1)
IN
3.3V CMOS PLL Multiplier select, logic for selecting
the multiply ratio for the PLL from the input REFCLK
16
VDD_OUT
PWR
3.3V supply for clock out puts
17
GND_OUT
PWR
Ground for clock outputs
18
BUSCLKC
OUT
Out put clock connected to the Rambus channel. This
output is the complement of BUSCLK
19
N/C
NOT USED
20
BUSCLKT
OUT
Output clock connected to the Rambus channel. This
output is the true component of BUSCLK
21
GND_OUT
PWR
Ground for clock outputs
22
VDD_OUT
PWR
3.3V supply for clock out puts
13,23,24
FS(0:2)
IN
3.3V CMOS Mode control, used in selecting bypass,
test, normal, and output test (OE)
相关PDF资料
PDF描述
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相关代理商/技术参数
参数描述
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