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参数资料
型号： 9250BF-28LF-T
厂商： INTEGRATED DEVICE TECHNOLOGY INC
元件分类： 时钟产生/分配
英文描述： 133.32 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封装： 0.300 INCH, GREEN, SSOP-56
文件页数： 17/19页
文件大小： 226K
代理商： 9250BF-28LF-T
7
ICS9250-28
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Maximum Case Operating Temperature . . . . . . +135°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
VIH
2VDD+0.3
V
Input Low Voltage
VIL
VSS-0.3
0.8
V
Input High Current
IIH
VIN = VDD
-5
5
A
IIL1
VIN = 0 V; Inputs with no pull-up resistors
-5
IIL2
VIN = 0 V; Inputs with pull-up resistors
-200
CL = 0 pF; @ 66/100 MHz
138
200
CL = 0 pF; @ 100/100 MHz
126
200
CL = 0 pF; @ 133/133 MHz
172
200
CL = 0 pF; @ 133/100 MHz
141
200
CL = Max loads; @ 66/100 MHz
339
400
CL = Max loads; @ 100/100 MHz
328
400
CL = Max loads; @ 133/133 MHz
383
450
CL = Max loads; @ 133/100 MHz
340
400
CL = 0 pF; @ 66/100 MHz
9
15
CL = 0 pF; @ 100/100 MHz
11
18
CL = 0 pF; @ 133/133 MHz
13
20
CL = 0 pF; @ 133/100 MHz
13
20
CL = Max loads; @ 66/100 MHz
13
35
CL = Max loads; @ 100/100 MHz
23
60
CL = Max loads; @ 133/133 MHz
29
60
CL = Max loads; @ 133/100 MHz
30
60
IDD3.3PD
CL = Max loads
251
400
IDD.25PD
Input address VDD or GND
<1
10
Input Frequency
Fi
VDD = 3.3 V
12
14.318
16
MHz
Transition time
1
Ttrans
To 1st crossing of target frequency
3
ms
Settling time
1
Ts
From 1st crossing to 1% target frequency
3
ms
Clk Stabilization
1
TSTAB
From VDD = 3.3 V to 1% target frequency
3
ms
tPZH,tPZL Output enable delay (all outputs)
1
10
ns
tPHZ,tPLZ Output disable delay (all outputs)
1
10
ns
1Guaranteed by design, not 100% tested in production.
Delay
1
mA
IDD2.5OP
A
Powerdown Current
Operating Supply
Current
Input Low Current
A
mA
IDD3.3OP
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相关代理商/技术参数
参数描述
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