参数资料
型号: 932S203AFLF
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟产生/分配
英文描述: 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封装: 0.300 INCH, GREEN, MO-118, SSOP-56
文件页数: 14/19页
文件大小: 284K
代理商: 932S203AFLF
4
ICS932S203
0601E—12/22/04
Byte 0: Control Register
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
3. The purpose of this bit is to allow a system designer to implement PCI_STOP functionality in one of two ways.
Wither the system designer can choose to use the externally provided PCI_STOP# pin to assert and de-assert
PCI_STOP functionality via SMBus Byte 0 Bit 3.
In Hardware mode it is not allowed to write to the SMBus Byte 0 Bit3. In Software mode it is not allowed to pull
the external PCI_STOP pin low. This avoids the issues related with Hardware started and software stopped
PCI_STOP conditions. The clock chip is to be operated in the Hardware or Software PCI_STOP mode ONLY, it
is not allowed to mix these modes.
In Hardware mode the SMBus byte 0 Bit 3 is R/W and should reflect the status of the part. Whether or not the
chip is in PCI_STOP mode.
Functionality PCI_STOP mode should be entered when [(PCI_STOP#=0) or (SMBus Byte 0 Bit 3 = 0)].
Byte 1: Control Register
t
i
B#
n
i
Pe
m
a
ND
W
Pe
p
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Tn
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p
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1
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B5
50
S
FX
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=
0
t
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Pe
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0
t
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B1
5
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2
5
0
T
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C
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0
C
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Rd
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l
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1
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D
=
0
1
t
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B8
4
,
9
4
1
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1
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=
1
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=
0
2
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4
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5
4
2
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1
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=
0
3
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5
,
2
50
-
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R
4
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40
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5
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6
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5
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3
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3
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b
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=
1
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=
0
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