参数资料
型号: 932S203YGLFT
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟产生/分配
英文描述: 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封装: 6.10 MM, 0.50 MM PITCH, GREEN, MO-153, TSSOP-56
文件页数: 13/18页
文件大小: 243K
代理商: 932S203YGLFT
IDTTM Frequency Generator with 133MHz Differential CPU Clocks
0601G—01/26/10
ICS932S203
Frequency Generator with 133MHz Differential CPU Clocks
4
Byte 0: Control Register
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
3. The purpose of this bit is to allow a system designer to implement PCI_STOP functionality in one of two ways. Wither the
system designer can choose to use the externally provided PCI_STOP# pin to assert and de-assert PCI_STOP
functionality via SMBus Byte 0 Bit 3.
In Hardware mode it is not allowed to write to the SMBus Byte 0 Bit3. In Software mode it is not allowed to pull the
external PCI_STOP pin low. This avoids the issues related with Hardware started and software stopped PCI_STOP
conditions. The clock chip is to be operated in the Hardware or Software PCI_STOP mode ONLY, it is not allowed to mix
these modes.
In Hardware mode the SMBus byte 0 Bit 3 is R/W and should reflect the status of the part. Whether or not the chip is in
PCI_STOP mode.
Functionality PCI_STOP mode should be entered when [(PCI_STOP#=0) or (SMBus Byte 0 Bit 3 = 0)].
Byte 1: Control Register
t
i
B#
n
i
Pe
m
a
ND
W
Pe
p
y
Tn
o
i
t
p
i
r
c
s
e
D
0
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
1
t
i
B5
50
S
FX
R
p
u
r
e
w
o
p
n
o
d
e
l
p
m
a
s
n
i
p
0
S
F
f
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e
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l
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h
t
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t
c
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l
f
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R
2
t
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B0
41
S
FX
R
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w
o
p
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d
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l
p
m
a
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p
1
S
F
f
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h
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R
3
t
i
B4
3#
P
O
T
S
_
I
C
P
3
XR
#
P
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T
S
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I
C
P
f
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R
:
e
d
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m
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w
d
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H
D
W
P
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l
p
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p
4
t
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B-
1
)
d
e
v
r
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s
e
R
(
5
t
i
B5
3H
C
V
/
1
_
6
V
30
W
R
z
H
M
8
4
/
z
H
M
6
t
c
e
l
e
S
H
C
V
z
H
M
8
4
=
1
,
z
H
M
6
=
0
6
t
i
B-
0
)
d
e
v
r
e
s
e
R
(
7
t
i
B-
d
a
e
r
p
S
d
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l
b
a
n
E
0W
Rn
O
d
a
e
r
p
S
=
1
,
f
O
d
a
e
r
p
S
=
0
t
i
B#
n
i
Pe
m
a
ND
W
Pe
p
y
Tn
o
i
t
p
i
r
c
s
e
D
0
t
i
B1
5
,
2
5
0
T
K
L
C
U
P
C
0
C
K
L
C
U
P
C
1W
Rd
e
l
b
a
n
E
=
1
d
e
l
b
a
s
i
D
=
0
1
t
i
B8
4
,
9
4
1
T
K
L
C
U
P
C
1
C
K
L
C
U
P
C
1W
Rd
e
l
b
a
n
E
=
1
d
e
l
b
a
s
i
D
=
0
2
t
i
B4
4
,
5
4
2
T
K
L
C
U
P
C
2
C
K
L
C
U
P
C
1W
Rd
e
l
b
a
n
E
=
1
d
e
l
b
a
s
i
D
=
0
3
t
i
B1
5
,
2
50
-
d
e
v
r
e
s
e
R
4
t
i
B8
4
,
9
40
-
d
e
v
r
e
s
e
R
5
t
i
B4
4
,
5
40
-
d
e
v
r
e
s
e
R
6
t
i
B4
5
,
3
5
3
T
K
L
C
U
P
C
3
C
K
L
C
U
P
C
1W
Rd
e
l
b
a
n
E
=
1
d
e
l
b
a
s
i
D
=
0
7
t
i
B3
40
L
E
S
T
L
U
MX
R
0
L
E
S
T
L
U
M
f
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R
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932S208DGLFT 功能描述:时钟合成器/抖动清除器 SERVER MAIN CLOCK RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel