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参数资料
| 型号： | 932S208DGLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封装： | 6.10 MM, 0.50 MM PITCH, GREEN, MO-153, TSSOP |
| 文件页数： | 16/22页 |
| 文件大小： | 231K |
| 代理商： | 932S208DGLFT |
3
Integrated
Circuit
Systems, Inc.
ICS932S208
0743D—07/07/04
Pin Description (Continued)
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
29
3V66_4/VCH
OUT
66.66MHz clock output for AGP support. AGP-PCI should be aligned
with a skew window tolerance of 500ps.
VCH is 48MHz clock output for video controller hub.
30
SDATA
I/O
Data pin for I2C circuitry 5V tolerant
31
48MHz_USB
OUT
48MHz clock output.
32
48MHz_DOT
OUT
48MHz clock output.
33
GND
PWR
Ground pin.
34
VDD48
PWR
Power pin for the 48MHz output.3.3V
35
Vtt_PWRGD#
IN
This 3.3V LVTTL input is a level sensitive strobe used to determine
when latch inputs are valid and are ready to be sampled. This is an
active low input.
36
VDD
PWR
Power supply for SRC clocks, nominal 3.3V
37
SRCCLKC
OUT
Complement clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
38
SRCCLKT
OUT
True clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
39
GND
PWR
Ground pin.
40
CPUCLKC0
OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
41
CPUCLKT0
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
42
VDDCPU
PWR
Supply for CPU clocks, 3.3V nominal
43
CPUCLKC1
OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
44
CPUCLKT1
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
45
GND
PWR
Ground pin.
46
CPUCLKC2
OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
47
CPUCLKT2
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
48
VDDCPU
PWR
Supply for CPU clocks, 3.3V nominal
49
CPUCLKC3
OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
50
CPUCLKT3
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
51
FS_A
IN
Frequency select pin, see Frequency table for functionality
52
IREF
OUT
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
53
GND
PWR
Ground pin.
54
GNDA
PWR
Ground pin for core.
55
VDDA
PWR
3.3V power for the PLL core.
56
FS_B
IN
Frequency select pin, see Frequency table for functionality
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 932S208YFLNT | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:Programmable Timing Control HubTM for Next Gen P4TM Processor |
| 932S208YGLNT | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:Programmable Timing Control HubTM for Next Gen P4TM Processor |
| 932S401EFLF | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| 932S401EFLFT | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| 932S401EGLF | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
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