- 您现在的位置：买卖IC网 > PDF目录24634 > 932S431AGLFT (INTEGRATED DEVICE TECHNOLOGY INC) 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 PDF资料下载
参数资料
| 型号： | 932S431AGLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封装： | 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-56 |
| 文件页数： | 11/22页 |
| 文件大小： | 226K |
| 代理商： | 932S431AGLFT |
19
Integrated
Circuit
Systems, Inc.
ICS932S431A
Datasheet
1426A—11/12/09
PD is an asynchronous active high input used to shut off all clocks cleanly prior to system power down.
When PD is asserted, all clocks will be driven low before turning off the VCO. All clocks will start without glitches when PD is
de-asserted.
PD, Power Down
D
PU
P
C#
U
P
CC
R
S#
C
R
SI
C
P
/
F
I
C
PB
S
UF
E
Re
t
o
N
0l
a
m
r
o
Nl
a
m
r
o
Nl
a
m
r
o
Nl
a
m
r
o
Nz
H
M
3
3z
H
M
8
4z
H
M
8
1
3
.
4
11
1r
o
2
*
f
e
r
I
t
a
o
l
F
t
a
o
l
F2
*
f
e
r
I
t
a
o
l
F
r
o
t
a
o
l
Fw
o
Lw
o
Lw
o
L1
Notes:
1. Refer to SMBus Byte 4 for additional information.
PD should be sampled high by 2 consecutive CPU# rising edges before stopping clocks. All single ended clocks will be held
low on their next high to low transition.
All differential clocks will be held high on the next high to low transition of the complimentary clock. If the control register
determining to drive mode is set to 'tri-state', the differential pair will be stopped in tri-state mode, undriven.
When the drive mode corresponding to the CPU or SRC clock of interest is set to '0' the true clock will be driven high at 2 x
Iref and the complementary clock will be tristated. If the control register is programmed to '1' both clocks will be tristated.
See SMBus Bytes 4 and 5 for additional information.
PD Assertion
PD
CPU, 133MHz
CPU#, 133MHz
SRC, 100MHz
SRC#, 100MHz
USB, 48MHz
PCI, 33MHz
REF, 14.31818
相关PDF资料 |
PDF描述 |
|---|---|
| 932S431AGLF | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 932S825YGLFT | 220 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO64 |
| 932S825YGT | 220 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO64 |
| 0550420000 | 25 A, MODULAR TERMINAL BLOCK, 1 DECK |
| 932S890CKLFT | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC72 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 932S801AFLF | 功能描述:IC K8 CLOCK CHIP 48-SSOP 制造商:idt, integrated device technology inc 系列:- 包装:管件 零件状态:过期 PLL:是 主要用途:服务器 输入:晶体 输出:时钟 电路数:1 比率 - 输入:输出:1：20 差分 - 输入:输出:无/是 频率 - 最大值:220MHz 电压 - 电源:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:48-BSSOP（0.295"，7.50mm 宽） 供应商器件封装:48-SSOP 标准包装:30 |
| 932S801AGLF | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| 932S801AGLFT | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| 932S805CGLF | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| 932S805CGLFT | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
发布紧急采购，3分钟左右您将得到回复。