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| 型号： | 933714130653 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 门电路 |
| 英文描述： | HC/UH SERIES, QUAD 2-INPUT NAND GATE, PDSO14 |
| 封装： | SOT-108-1, SO-14 |
| 文件页数： | 5/12页 |
| 文件大小： | 158K |
| 代理商： | 933714130653 |
September 1993
2
Philips Semiconductors
Product specication
Quad 2-input NAND Schmitt trigger
74HC/HCT132
FEATURES
Output capability: standard
ICC category: SSI
GENERAL DESCRIPTION
The 74HC/HCT132 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT132 contain four 2-input NAND gates which accept standard input signals. They are capable of
transforming slowly changing input signals into sharply defined, jitter-free output signals.
The gate switches at different points for positive and negative-going signals. The difference between the positive voltage
VT+ and the negative voltage VT is defined as the hysteresis voltage VH.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf = 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD =CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPHL/ tPLH
propagation delay nA, nB to nY
CL = 15 pF; VCC =5 V 11
17
ns
CI
input capacitance
3.5
pF
CPD
power dissipation capacitance per gate
notes 1 and 2
24
20
pF
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