- 您现在的位置：买卖IC网 > PDF目录24769 > 935049490602 (NXP SEMICONDUCTORS) F/FAST SERIES, 4-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16 PDF资料下载
参数资料
| 型号： | 935049490602 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 计数移位寄存器 |
| 英文描述： | F/FAST SERIES, 4-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16 |
| 封装： | PLASTIC, SOT-109, SO-16 |
| 文件页数： | 3/13页 |
| 文件大小： | 151K |
| 代理商： | 935049490602 |
file:///G|/imaging/BITTING/CPL/20030424/04232003_9/PHGL/_HTML04232003/N74F195AD.html
Product Information
74F195A; 4-bit
parallel-access shift
register
Information as of 2003-04-22
Stay informed
Download datasheet
Support & tools
topGeneral description
The 74F195A is a 4-Bit Parallel Access Shift Register and its functional characteristics are indicated in the
Logic Diagram and Function Table. This device is useful in a variety of shifting, counting and storage
applications. It performs serial, parallel, serial to parallel, or parallel to serial data transfers at very high speeds.
The 74F195A operates in two primary modes: shift right (Q0
→Q1) and parallel load, which are controlled by
the state of the Parallel Enable (PE) input. Serial data enters the first flip-flop (Q0) via the J and K inputs when
the PE input is High, and is shifted one bit in the direction Q0
→Q1→Q2→Q3 following each Low-to-High
clock transition.
The J and K inputs provide the flexibility of the J-K type input for special applications, and by tying the two
together the simple D-type input is made for general applications.
The device appears as four common clocked D flip-flops when the PE input is Low. After the Low-to-High
clock transition, data on the parallel inputs (D0–D3) is transferred to the respective Q0–Q3 outputs. Shift left
operation (Q3–Q2) can be achieved by tying the Qn outputs to the Dn-1 inputs and holding the PE input Low.
All parallel and serial data transfers are synchronous, occurring after each Low-to-High clock transition. The
74F195A utilizes edge-triggering, therefore there is no restriction on the activity of the J, K, Dn, and PE inputs
for logic operation, other than the set-up and hold time requirements.
A Low on the asynchronous Master Reset (MR) input sets all Q outputs Low, independent of any other input
condition.
topFeatures
q
Shift right and parallel load capability
q
J – K (D) inputs to first stage
q
Complement output from last stage
q
Asynchronous Master Reset
q
Diode inputs
file:///G|/imaging/BITTING/CPL/20030424/04232003_9/PHGL/_HTML04232003/N74F195AD.html (1 of 3) [May-08-2003 4:41:00 PM]
Submit Query
相关PDF资料 |
PDF描述 |
|---|---|
| 935049500602 | F/FAST SERIES, 4-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP16 |
| 0643241149 | 1 mm2, COPPER ALLOY, GOLD FINISH, WIRE TERMINAL |
| 935051240112 | HCT SERIES, OCTAL 1-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24 |
| 935051240118 | HCT SERIES, OCTAL 1-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24 |
| 935051260112 | HC/UH SERIES, OCTAL 1-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDIP24 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 9350-4R1 | 制造商:Johanson Manufacturing 功能描述:VARIABLE CAPACITOR 制造商:Johanson 功能描述:VARIABLE CAPACITOR |
| 9350524523211N | 制造商:ESSEX 功能描述:ESSEX 32V/DC |
| 9350569 | 制造商:WIKA INSTRUMENTS 功能描述:1/8,1/4 GAUGE |
| 93505A180 | 制造商:MISC. SPCR/STNDF/HND 功能描述: |
| 93505A43 | 制造商:FLORIDA MISC. 功能描述: 制造商:Florida Misc. 功能描述: |
发布紧急采购，3分钟左右您将得到回复。