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参数资料
| 型号： | 935049500602 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 计数移位寄存器 |
| 英文描述： | F/FAST SERIES, 4-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP16 |
| 封装： | 0.300 INCH, PLASTIC, SOT-38-4, DIP-16 |
| 文件页数： | 10/13页 |
| 文件大小： | 151K |
| 代理商： | 935049500602 |
Philips Semiconductors
Product specification
74F195A
4-bit parallel-access shift register
1996 Mar 12
6
AC SETUP REQUIREMENTS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
VCC = +5V
Tamb = +25°C
CL = 50pF, RL = 500
VCC = +5V ± 10%
Tamb = 0°C to +70°C
CL = 50pF, RL = 500
UNIT
MIN
TYP
MAX
MIN
MAX
tS(H)
tS(L)
Setup time, High or Low
J, K and Dn to CP
Waveform 3
2.5
ns
th(H)
th(L)
Hold time, High or Low
J, K and Dn to CP
Waveform 3
0.0
1.0
0.0
1.0
ns
tS(H)
tS(L)
Setup time, High or Low
PE to CP
Waveform 4
2.0
2.5
2.0
2.5
ns
th(H)
th(L)
Hold time, High or Low
PE to CP
Waveform 4
0.0
ns
tW(H)
CP Pulse width
High
Waveform
NO TAG
4.5
ns
tW(L)
MR Pulse width
Low
Waveform 2
4.5
ns
tREC
Recovery time
MR to CP
Waveform 2
2.5
3.0
ns
AC WAVEFORMS
For all waveforms, VM = 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
tPHL
tPLH
CP
VM
tw(H)
1/fmax
VM
tPLH
Q3
VM
Qn
tPHL
SF00761
Waveform 1.
Propagation Delay, Clock Input to Output,
Clock Pulse Width, and Maximum Clock Frequency
th(H)
ts(H)
CP
SF00763
VM
th(L)
ts(L)
J, K,
Dn
Waveform 2.
Data Setup and Hold Times
CP
VM
tPHL
trec
MR
Qn
tw(L)
VM
Q3
tPLH
SF00762
Waveform 3.
Master Reset Pulse Width, Master Reset to
Output Delay, and Master Reset to Clock Recovery Time
CP
VM
PE
Qn
ts(H)
SF00764
th
ts(L)
RESPONSE
Qn=Qn–1
Qn=Dn
SERIAL-SHIFT RIGHT
PARALLEL LOAD
th
Waveform 4.
Setup and Hold Times, Parallel Enable to Clock
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