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参数资料
| 型号： | 935052330602 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 锁存器 |
| 英文描述： | F/FAST SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20 |
| 封装： | 7.50 MM, PLASTIC, MS-013AC, SOT-163-1, SOL-20 |
| 文件页数： | 6/13页 |
| 文件大小： | 161K |
| 代理商： | 935052330602 |
Philips Semiconductors
Product specification
74F377A
Octal D-type flip-flop with enable
2
1996 Mar 12
853–0026 16555
FEATURES
High impedance inputs for reduced loading (20A in Low and
High states)
Ideal for addressable register applications
Enable for address and data synchronization applications
Eight edge–triggered D–type flip–flops
Buffered common clock
See ’F273A for Master Reset version
See ’F373 for transparent latch version
See ’F374 for 3–State version
DESCRIPTION
The 74F377A has 8 edge-triggered D-type flip-flops with individual D
inputs and Q outputs. The common buffered clock (CP) input loads
all flip-flops simultaneously when the Enable (E) input is Low.
The register is fully edge triggered. The state of each D input, one
set-up time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop’s Q output.
The E input must be stable one setup time prior to the Low-to-High
clock transition for predictable operation.
TYPE
TYPICAL fMAX
TYPICAL SUPPLY CURRENT (TOTAL)
74F377A
165MHz
29mA
ORDERING INFORMATION
PACKAGES
COMMERCIAL RANGE
VCC = 5V±10%; Tamb = 0°C to +70°C
PKG. DWG. #
20–pin plastic DIP
N74F377AN
SOT146-1
20–pin plastic SOL
N74F377AD
SOT163-1
INPUT AND OUTPUT LOADING AND FAN–OUT TABLE
PINS
DESCRIPTION
74F(U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
D0 – D7
Data inputs
1.0/0.033
20
A/20A
CP
Clock pulse input (active rising edge)
1.0/0.033
20
A/20A
E
Enable input (active–Low)
1.0/0.033
20
A/20A
Q0 – Q7
Data outputs
50/33
1.0mA/20mA
PIN CONFIGURATION
20
19
18
17
16
15
14
13
12
10
11
9
8
7
6
5
4
3
2
1
VCC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CP
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
E
SF00350
LOGIC SYMBOL
SF00351
3
4
7
8
13
14
18
17
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
1
11
E
CP
VCC = Pin 20
GND = Pin 10
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