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参数资料
| 型号： | 935262009112 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封装： | 5.30 MM, PLASTIC, MO-150AH, SOT-341-1, SSOP-28 |
| 文件页数： | 7/12页 |
| 文件大小： | 81K |
| 代理商： | 935262009112 |
Philips Semiconductors
Product specification
PCK2000M
CK97 (66/100MHz) Mobile System Clock Generator
1998 Sep 29
4
SELECT FUNCTIONS
SEL100/66
SEL0
FUNCTION
NOTES
0
TRI-State
1
0
1
Active 66MHz
1
0
Test mode
1
Active 100MHz
NOTES:
1. Internal decode logic for all two select inputs implemented.
FUNCTION
OUTPUTS
DESCRIPTION
CPU
PCI, PCI_F
REF
Tri-State
Hi-Z
Test mode
TCLK/2
TCLK/6
TCLK
FUNCTION TABLE
SEL 100/66
CPU/PCI RATIO
CPUCLK (0–1)
(MHz)
CPICLK (1–5)
PCICLK_F
(MHz)
REF
(MHz)
0
2
66.66
33.33
14.318
1
3
100
33.33
14.318
CLOCK ENABLE CONFIGURATION
CPUSTOP
PCISTOP
PWRDWN
CPUCLK
PCICLK
PCICLK_F
OTHER
CLOCKS
PLL
OSCILLATOR
X
0
LOW
Stopped
OFF
0
1
LOW
33MHz
Running
0
1
LOW
33MHz
Running
1
0
1
100/66MHz
LOW
33MHz
Running
1
100/66MHz
33MHz
Running
POWER MANAGEMENT REQUIREMENTS
LATENCY
SIGNAL
SIGNAL STATE
NO. OF RISING EDGES OF FREE RUNNING
PCICLK
CPUSTOP
0 (DISABLED)
1
1 (ENABLED)
1
PCISTOP
0 (DISABLED)
1
1 (ENABLED)
1
PWRDWN
1 (NORMAL OPERATION)
3ms
0 (POWER DOWN)
2 MAX
NOTES:
1. Clock ON/OFF latency is defined as the number of rising edges of free running PCICLKs between the clock disable goes HIGH/LOW to the
first valid clock that comes out of the device.
2. Power up latency is when PWRDWN goes inactive (HIGH) to when the first valid clocks are driven from the device.
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