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参数资料
| 型号： | 935269132112 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封装： | 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48 |
| 文件页数： | 12/15页 |
| 文件大小： | 113K |
| 代理商： | 935269132112 |
Philips Semiconductors
Product data
PCKV857
70–190 MHz differential 1:10 clock driver
2002 Sep 13
6
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIK
Input voltage, all inputs
VDDQ = 2.3 V, II = –18 mA
—
1.2
V
VO
High level output voltage
VDDQ = min to max, IOH = –1 mA
VDDQ 0.1
—
V
VOH
High-level output voltage
VDDQ = 2.3 V, IOH = –12 mA
1.7
—
V
VO
Low level output voltage
VDDQ = min to max, IOL = 1 mA
—
0.1
V
VOL
Low-level output voltage
VDDQ = 2.3 V, IOL = 12 mA
—
0.6
V
II
Input current
VDDQ = 2.7 V, VI = 0 V to 2.7 V
—
±10
A
IOZ
High-impedance-state output current
VDDQ = 2.7 V, VO = VDDQ or GND
—
±10
A
IDDPD
Power-down current on VDDQ + AVDD
CLK and CLK = 0 MHz,
PWRDWN = low;
Σ of IDD and AIDD
—
30
100
A
IDD
Dynamic current on VDDQ
fO = 67 MHz to 190 MHz
—
200
300
mA
AIDD
Supply current on AVDD
fO = 67 MHz to 190 MHz
—
8
10
mA
CI
Input capacitance
VCC = 2.5 V, VI = VCC or GND
2
2.8
3
pF
NOTE:
1. This is intended to operate in the SSTL_2 type IV unterminated mode without series resistors on the outputs.
2. All typical values are at respective nominal VDDQ.
3. Differential cross-point voltage is expected to track variations of VDDQ and is the voltage at which the differential signals must be crossing.
TIMING REQUIREMENTS
Over recommended ranges of supply voltage and operating free-air temperature.
SYMBOL
PARAMETER
MIN
MAX
UNIT
fCK
Operating clock frequency
60
190
MHz
Input clock duty cycle
40
60
%
Stabilization time1
100
—
s
NOTE:
1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power-up.
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