参数资料
型号: 935269824112
厂商: NXP SEMICONDUCTORS
元件分类: Buffer和线驱动
英文描述: LINE TRANSCEIVER, PDSO16
封装: 4.40 MM, PLASTIC, MO-153, SOT-403-1, TSSOP-16
文件页数: 6/25页
文件大小: 594K
代理商: 935269824112
Philips Semiconductors
ISP1105/1106/1107
Advanced USB transceivers
Product data
Rev. 07 — 29 March 2002
14 of 25
9397 750 09529
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
11. Dynamic characteristics
Table 16:
Dynamic characteristics: analog I/O pins (D
+, D)[1]
VCC = 4.0 to 5.5 V or Vreg(3.3) = 3.0 to 3.6 V; VCC(I/O) = 1.65 to 3.6 V; VGND = 0 V; see Table 10 for valid voltage level
combinations; Tamb = 40 to +85 °C; unless otherwise specied.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Driver characteristics
Full-speed mode (SPEED = HIGH)
tFR
rise time
CL = 50 to 125 pF;
10 to 90% of
|VOH VOL|;
4
-
20
ns
tFF
fall time
CL = 50 to 125 pF;
90 to 10% of
|VOH VOL|;
4
-
20
ns
FRFM
differential rise/fall time
matching (tFR/tFF)
excluding the rst transition
from Idle state
90
-
111.1
%
VCRS
output signal crossover
voltage
excluding the rst transition
from Idle state; see Figure 9
[2] 1.3
-
2.0
V
Low-speed mode (SPEED = LOW)
tLR
rise time
CL = 50 to 600 pF;
10 to 90% of
|VOH VOL|;
75
-
300
ns
tLF
fall time
CL = 50 to 600 pF;
90 to 10% of
|VOH VOL|;
75
-
300
ns
LRFM
differential rise/fall time
matching (tLR/tLF)
excluding the rst transition
from Idle state
80
-
125
%
VCRS
output signal crossover
voltage
excluding the rst transition
from idle state; see Figure 9
[2] 1.3
-
2.0
V
Driver timing
Full-speed mode (SPEED = HIGH)
tPLH(drv)
driver propagation delay
LOW-to-HIGH; see Figure 9
--18
ns
tPHL(drv)
(VO/VPO, FSE0/VMO to
D
+,D)
HIGH-to-LOW; see Figure 9
--18
ns
tPHZ
driver disable delay
HIGH-to-OFF; see Figure 7
--15
ns
tPLZ
(OE to D
+,D)
LOW-to-OFF; see Figure 7
--15
ns
tPZH
driver enable delay
OFF-to-HIGH; see Figure 7
--15
ns
tPZL
(OE to D
+,D)
OFF-to-LOW; see Figure 7
--15
ns
Low-speed mode (SPEED = LOW)
Not specied: low-speed delay timings are dominated by the slow rise/fall times tLR and tLF.
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