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参数资料
| 型号： | 93718CFLF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 93718 SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 12 INVERTED OUTPUT(S), PDSO48 |
| 封装： | 0.300 INCH, ROHS COMPLIANT, MO-118, SSOP-48 |
| 文件页数： | 1/9页 |
| 文件大小： | 96K |
| 代理商： | 93718CFLF |
ICS93718
IDTTM/ICSTM DDR and SDRAM buffer
ICS93718
REV E 02/11/07
DDR and SDRAM Buffer
DATASHEET
Description
Output Features
DDR & SDRAM fanout buffer, for VIA Pro 266, KT266 and P4X266
DDR chipsets
Low skew, fanout buffer
1 to 12 differential clock distribution
I
2C for functional and output control
Feedback pin for input to output synchronization
Supports up to 4 DDR DIMMs or 3 SDRAM DIMMs + 2
DDR DIMMs
Frequency supports up to 200MHz (DDR400)
Supports Power Down Mode for power mananagement
CMOS level control signal input
Key Specifications
OUTPUT - OUTPUT skew: <100ps
Output Rise and Fall Time for DDR outputs: 500ps - 700ps
DUTY CYCLE: 47% - 53%
48-pin SSOP package
Available in RoHS compliant packaging
Pin Configuration
Funtional Block Diagram
48-Pin SSOP
FB_OUT
VDD3.3_2.5
GND
DDRT0_SDRAM0
DDRC0_SDRAM1
DDRT1_SDRAM2
DDRC1_SDRAM3
VDD3.3_2.5
GND
DDRT2_SDRAM4
DDRC2_SDRAM5
VDD3.3_2.5
BUF_IN
GND
DDRT3_SDRAM6
DDRC3_SDRAM7
VDD3.3_2.5
GND
DDRT4_SDRAM8
DDRC4_SDRAM9
DDRT5_SDRAM10
DDRC5_SDRAM11
VDD3.3_2.5
SDATA
SEL_DDR*
VDD2.5
GND
DDRT11
DDRC11
DDRT10
DDRC10
VDD2.5
GND
DDRT9
DDRC9
VDD2.5
PD#*
GND
DDRT8
DDRC8
VDD2.5
GND
DDRT7
DDRC7
DDRT6
DDRC6
GND
SCLK
ICS93718
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
*Internal Pull-up Resistor of 120K to VDD
SCLK
SDATA
SEL_DDR*
PD#
BUF_IN
Control
Logic
FB_OUT
DDRT0_SDRAM0
DDRT1_SDRAM2
DDRT2_SDRAM4
DDRT3_SDRAM6
DDRT4_SDRAM8
DDRT5_SDRAM10
DDRT(11:6)
DDRC0_SDRAM1
DDRC1_SDRAM3
DDRC2_SDRAM5
DDRC3_SDRAM7
DDRC4_SDRAM9
DDRC5_SDRAM11
DDRC (11:6)
Funtionality Table
E
D
O
M8
4
N
I
P
D
V
5
.
2
_
3
.
3
N
I
P
,
5
1
,
1
,
0
1
,
7
,
6
,
5
,
4
2
,
1
2
,
0
2
,
9
1
,
6
1
R
D
e
d
o
M
1
=
R
D
_
L
E
SV
5
.
2
e
b
ll
i
w
s
t
u
p
t
u
o
e
s
e
h
T
s
t
u
p
t
u
o
R
D
S
/
R
D
e
d
o
M
0
=
R
D
_
L
E
SV
3
.
3
e
b
ll
i
w
s
t
u
p
t
u
o
e
s
e
h
T
M
A
R
D
S
d
r
a
d
n
a
t
s
t
u
p
t
u
o
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