参数资料
| 型号： | 93C56C-I/P |
| 厂商： | Microchip Technology |
| 文件页数： | 11/36页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 2KBIT 3MHZ 8DIP |
| 标准包装： | 60 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 2K（256 x 8 或 128 x 16） |
| 速度： | 3MHz |
| 接口： | Microwire 3 线串行 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 8-PDIP |
| 包装： | 管件 |
| 产品目录页面： | 1451 (CN2011-ZH PDF) |
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93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
2.9 Write All (WRAL)
The Write All ( WRAL ) instruction will write the entire
memory array with the data specified in the command.
For 93AA56A/B/C and 93LC56A/B/C devices, after the
last data bit is clocked into DI, the falling edge of CS
initiates the self-timed auto-erase and programming
cycle. For 93C56A/B/C devices, the self-timed auto-
erase and programming cycle is initiated by the rising
edge of CLK on the last data bit. Clocking of the CLK
pin is not necessary after the device has entered the
WRAL cycle. The WRAL command does include an
automatic ERAL cycle for the device. Therefore, the
WRAL instruction does not require an ERAL instruction,
but the chip must be in the EWEN status.
The DO pin indicates the Ready/ Busy status of the
device if CS is brought high after a minimum of 250 ns
low (T CSL ).
Note: After the Write All cycle is complete,
issuing a Start bit and then taking CS low
will clear the Ready/ Busy status from DO.
V CC must be ? 4.5V for proper operation of WRAL.
FIGURE 2-10:
WRAL TIMING FOR 93AA AND 93LC DEVICES
T CSL
CS
CLK
DI
1
0
0
0
1
x
???
x
Dx
???
D0
T SV
T CZ
DO
High-Z
Busy
Ready
H IGH -Z
T WL
V CC must be ? 4.5V for proper operation of WRAL.
FIGURE 2-11:
WRAL TIMING FOR 93C DEVICES
T CSL
CS
CLK
DI
1
0
0
0
1
x
???
x
Dx
???
D0
T SV
T CZ
DO
High-Z
Busy
Ready
H IGH -Z
T WL
? 2003-2011 Microchip Technology Inc.
DS21794G-page 11
相关PDF资料 |
PDF描述 |
|---|---|
| APA600-CGS624B | IC FPGA PROASIC+ 600K 624-CGA |
| 93AA56C-I/P | IC EEPROM 2KBIT 3MHZ 8DIP |
| 93C66CT-I/ST | IC EEPROM 4KBIT 3MHZ 8TSSOP |
| 93LC56A-E/SN | IC EEPROM 2KBIT 3MHZ 8SOIC |
| EP2S130F1020I4N | IC STRATIX II FPGA 130K 1020FBGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 93C56CMS | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:2K Microwire Compatible Serial EEPROM |
| 93C56CP | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:2K Microwire Compatible Serial EEPROM |
| 93C56CSN | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:2K Microwire Compatible Serial EEPROM |
| 93C56CST | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:2K Microwire Compatible Serial EEPROM |
| 93C56CT-E/CH | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:1K-16K Microwire Compatible Serial EEPROMs |
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