参数资料
型号: 93C66C-I/P
厂商: Microchip Technology
文件页数: 11/38页
文件大小: 0K
描述: IC EEPROM 4KBIT 3MHZ 8DIP
标准包装: 60
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 4K(512 x 8 或 256 x 16)
速度: 3MHz
接口: Microwire 3 线串行
电源电压: 4.5 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-DIP(0.300",7.62mm)
供应商设备封装: 8-PDIP
包装: 管件
产品目录页面: 1452 (CN2011-ZH PDF)
其它名称: 93C66C-I/PR
93C66C-I/PR-ND
93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
2.9 Write All (WRAL)
The Write All ( WRAL ) instruction will write the entire
memory array with the data specified in the command.
For 93AA66A/B/C and 93LC66A/B/C devices, after the
last data bit is clocked into DI, the falling edge of CS
initiates the self-timed auto-erase and programming
cycle. For 93C66A/B/C devices, the self-timed auto-
erase and programming cycle is initiated by the rising
edge of CLK on the last data bit. Clocking of the CLK
pin is not necessary after the device has entered the
WRAL cycle. The WRAL command does include an
automatic ERAL cycle for the device. Therefore, the
WRAL instruction does not require an ERAL instruction,
but the chip must be in the EWEN status.
The DO pin indicates the Ready/ Busy status of the
device if CS is brought high after a minimum of 250 ns
low (T CSL ).
Note: Issuing a Start bit and then taking CS low
will clear the Ready/ Busy status from DO.
V CC must be ? 4.5V for proper operation of WRAL.
FIGURE 2-10:
WRAL TIMING FOR 93AA AND 93LC DEVICES
T CSL
CS
CLK
DI
1
0
0
0
1
x
???
x
Dx
???
D0
T SV
T CZ
DO
High-Z
Busy
Ready
H IGH -Z
T WL
V CC must be ? 4.5V for proper operation of WRAL.
FIGURE 2-11:
WRAL TIMING FOR 93C DEVICES
T CSL
CS
CLK
DI
1
0
0
0
1
x
???
x
Dx
???
D0
T SV
T CZ
DO
High-Z
Busy
Ready
H IGH -Z
T WL
? 2003-2011 Microchip Technology Inc.
DS21795E-page 11
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