参数资料
| 型号： | 93C76T-E/SN |
| 厂商： | Microchip Technology |
| 文件页数： | 6/20页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 8KBIT 2MHZ 8SOIC |
| 标准包装： | 3,300 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 8K（1K x 8 或 512 x 16） |
| 速度： | 2MHz |
| 接口： | Microwire 3 线串行 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 带卷 (TR) |
93C76/86
3.0
DEVICE OPERATION
3.4
Erase All (ERAL)
3.1
Read
The ERAL instruction will erase the entire memory array
to the logical “ 1 ” state. The ERAL cycle is identical to
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 16-bit (x16 organization) or 8-bit
(x8 organization) output string. The output data bits will
toggle on the rising edge of the CLK and are stable
after the specified time delay (T PD ). Sequential read is
possible when CS is held high and clock transitions
continue. The memory address pointer will automati-
cally increment and output data sequentially.
the erase cycle except for the different opcode. The
ERAL cycle is completely self-timed and commences
on the rising edge of the last address bit (A0). Note that
the Least Significant 8 or 9 address bits are "don’t care"
bits, depending on selection of x16 or x8 mode. Clock-
ing of the CLK pin is not necessary after the device has
entered the self clocking mode. The ERAL instruction is
ensured at Vcc = +4.5V to +5.5V.
The DO pin indicates the Ready/Busy status of the
device if the CS is high. The Ready/Busy status will be
3.2
Erase
displayed on the DO pin until the next Start bit is
received as long as CS is high. Bringing the CS low will
The ERASE instruction forces all data bits of the
specified address to the logical “ 1 ” state. The self-timed
programming cycle is initiated on the rising edge of
CLK as the last address bit (A0) is clocked in. At this
point, the CLK, CS and DI inputs become “don’t cares”.
The DO pin indicates the Ready/Busy status of the
device if the CS is high. The Ready/Busy status will be
place the device in Standby mode and cause the DO
pin to enter the high-impedance state. DO at logical “ 0 ”
indicates that programming is still in progress. DO at
logical “ 1 ” indicates that the entire device has been
erased and is ready for another instruction.
The ERAL cycle takes 15 ms maximum (8 ms typical).
displayed on the DO pin until the next Start bit is
received as long as CS is high. Bringing the CS low will
3.5
Write All (WRAL)
place the device in Standby mode and cause the DO
pin to enter the high-impedance state. DO at logical “ 0 ”
indicates that programming is still in progress. DO at
logical “ 1 ” indicates that the register at the specified
address has been erased and the device is ready for
another instruction.
The erase cycle takes 3 ms per word (typical).
The WRAL instruction will write the entire memory array
with the data specified in the command. The WRAL
cycle is completely self-timed and commences on the
rising edge of the last address bit (A0). Note that the
Least Significant 8 or 9 address bits are “don’t cares”,
depending on selection of x16 or x8 mode. Clocking of
the CLK pin is not necessary after the device has
entered the self clocking mode. The WRAL command
3.3
Write
does include an automatic ERAL cycle for the device.
Therefore, the WRAL instruction does not require an
The WRITE instruction is followed by 16 bits (or by 8
bits) of data to be written into the specified address.
The self-timed programming cycle is initiated on the
rising edge of CLK as the last data bit (D0) is clocked
in. At this point, the CLK, CS and DI inputs become
“don’t cares”.
The DO pin indicates the Ready/Busy status of the
device if the CS is high. The Ready/Busy status will be
displayed on the DO pin until the next Start bit is
received as long as CS is high. Bringing the CS low will
place the device in Standby mode and cause the DO
pin to enter the high-impedance state. DO at logical “ 0 ”
indicates that programming is still in progress. DO at
logical “ 1 ” indicates that the register at the specified
address has been written and the device is ready for
another instruction.
The write cycle takes 3 ms per word (typical).
DS21132E-page 6
ERAL instruction but the chip must be in the EWEN
status. The WRAL instruction is ensured at Vcc = +4.5V
to +5.5V.
The DO pin indicates the Ready/Busy status of the
device if the CS is high. The Ready/Busy status will be
displayed on the DO pin until the next Start bit is
received as long as CS is high. Bringing the CS low will
place the device in Standby mode and cause the DO
pin to enter the high-impedance state. DO at logical “ 0 ”
indicates that programming is still in progress. DO at
logical “ 1 ” indicates that the entire device has been
written and is ready for another instruction.
The WRAL cycle takes 30 ms maximum (16 ms
typical).
? 2004 Microchip Technology Inc.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 93C76T-I/P | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:8K/16K 5.0V Microwire Serial EEPROM |
| 93C76T-I/SN | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:8K/16K 5.0V Microwire Serial EEPROM |
| 93C86 | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:8K/16K 5.0V Microwire Serial EEPROM |
| 93C86-/P | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:8K/16K 5.0V Microwire Serial EEPROM |
| 93C86-/SN | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:8K/16K 5.0V Microwire Serial EEPROM |
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