参数资料
型号: 93L34DMQB
厂商: NATIONAL SEMICONDUCTOR CORP
元件分类: 锁存器
英文描述: 93L SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDIP16
封装: CERAMIC, DIP-16
文件页数: 3/8页
文件大小: 112K
代理商: 93L34DMQB
Switching Characteristics VCC ea50V TA ea25 C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
CL e 15 pF
Units
Min
Max
tPLH
Propagation Delay
45
ns
tPHL
E to Qn
42
tPLH
Propagation Delay
65
ns
tPHL
DtoQn
45
tPLH
Propagation Delay
66
ns
tPHL
An to Qn
66
tPHL
Propagation Delay
55
ns
CL to Qn
Functional Description
The 93L34 has four modes of operation which are shown in
the Mode Select Table In the addressable latch mode data
on the data line (D) is written into the addressed latch The
addressed latch will follow the Data input with all non-ad-
dressed latches remaining in their previous states In the
memory mode all latches remain in their previous state and
are unaffected by the data or address inputs To eliminate
the possibility of entering erroneous data into the latches
the Enable should be held HIGH while the Address lines are
changing In the 1-of-8 decoding or demultiplexing mode
the addressed output will follow the state of the D input with
all other outputs in the LOW state In the clear mode all
outputs are LOW and unaffected by the address and data
inputs When operating the 93L34 as an addressable latch
changing more than one bit of the address could impose a
transient wrong address Therefore this should only be
done while in the memory mode
Mode Select Table
E
CL
Mode
L
H
Addressable Latch
H
Memory
L
Active HIGH 8-Channel Demultiplexer
H
L
Clear
3
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